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? 6024 silver creek valley road, san jose, california 95138 telephone: (800) 345-7015 ? (408) 284-8200 ? fax: (408) 284-2775 printed in u.s.a. ?2009 integrated device technology, inc. powerspan ii ? user manual 80a1010_ma001_09 november 2009
general disclaimer integrated device technology, inc. reserves the right to make changes to its products or specifications at any time, without no tice, in order to improve design or performance and to supply the best possible product. id t does not assume any responsibility for us e of any circuitry described other than t he circuitry embodied in an idt product. the company makes no representations that circuitry described herein is free from pat ent infringement or other rights of third part ies which may result from its use. no license is granted by implication or otherwise under any patent, patent rights or other rights, of integrated device technology, inc. code disclaimer code examples provided by idt are for ill ustrative purposes only and should not be relied upon for developing applications. any use of the code examples below is completely at your own risk. idt makes no representations or warranties of any kind concerning the noninfringement, quality, safety or sui tability of the code, either express or implied, including without limi tation any implied warranties of merchantability, fitness for a p articu- lar purpose, or non-infringement. further, idt makes no represen tations or warranties as to the truth, accuracy or completeness of any statements, information or materials concerning code exam ples contained in any idt publication or public disclosure or that is contained on any idt internet site. in no event will idt be liable for any direct, consequential, incidental, indirect, punitive or special damages, however they may arise, and even if idt has been previously advised about the possibility of such damages. the code examples also may be subject to united stat es export control laws and may be subject to the export or import laws of other coun tries and it is your res ponsibility to comply with any applicable laws or regulations. life support policy integrated device technology's products are not authorized for us e as critical components in life support devices or systems un less a specific written agreement pertaining to such intended use is executed between t he manufacturer and an officer of idt. 1. life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) supp ort or sustain life and whose failure to perform, when properly used in accordance with instru ctions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any components of a life support device or system whose failure to per form can be reasonably expecte d to cause the failure of the life support device or system, or to affect its safety or effectiveness. idt, the idt logo, and integrated device technology are trademarks or registered trademarks of int egrated device technology, in c.
powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 3 contents 1. functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1.1 powerspan ii features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.1.2 powerspan ii benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1.3 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.1.4 powerspan ii and powerspan differences summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.2 pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.2.1 pci-to-pci bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.2.2 primary pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.2.3 pci host bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.2.4 pci bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.3 processor bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.3.1 address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.3.2 processor bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5 i2c / eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.1 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.2 i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6 concurrent reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6.1 powerspan ii?s concurrent read solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6.2 powerspan ii?s concurrent read app lications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2. pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.1.1 primary pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.1.2 pci data width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.1.3 pci interface descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.1.4 transaction ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2 pci target interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.1 address phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.2 data phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.2.3 termination phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.3 pci master interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.3.1 arbitration phase: arbitration for the pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.3.2 address phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.3.3 data phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.3.4 terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.4 compactpci hot swap silicon support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.4.1 led support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.4.2 es input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.4.3 healthy# signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.4.4 compactpci hot swap card insertion and extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.4.5 hot swap insertion process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.4.6 hot swap extraction process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
contents 4 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.5 vital product data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.5.1 vpd access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.5.2 reading vpd data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.5.3 writing vpd data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.6 i2o shell interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.6.1 i2o target image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.6.2 iop functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.6.3 messaging interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.6.4 inbound messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.6.5 outbound messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.6.6 pull capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 2.6.7 outbound option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 2.6.8 i2o standard registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3. processor bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 3.2 interface support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.2.1 terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.2.2 pb bus interface descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.3 pb slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.3.1 address phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.3.2 data phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.3.3 terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.4 pb master interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.4.1 address phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.4.2 data phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.4.3 terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 4. dma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 4.2 dma register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 4.2.1 source and destination addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 4.2.2 transfer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.2.3 command packet addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.2.4 address retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.2.5 general dma control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.2.6 processor bus transfer attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.3 direct mode dma operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.3.1 initializing a direct mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.4 linked-list mode dma operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.4.1 initializing a linked-list mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.5 dma interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.6 dma error handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.6.1 pci error bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.6.2 processor bus error bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.6.3 source port errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.6.4 destination port errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.6.5 command port errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com contents 5 5. i2c/eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.2 power-up configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.2.1 eeprom loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.3 bus master i 2 c transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.4 pci vital product data (vpd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6. arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 6.2 pci interface arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.2.1 arbitration levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.2.2 bus parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.3 processor bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.3.1 address bus arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3.2 data bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3.3 address only cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.3.4 powerspan ii arbiter and system boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7. interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.2 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.2.1 interrupts from normal operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.2.2 interrupts from transaction exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 7.3 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 7.3.1 interrupt status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 7.3.2 interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 7.3.3 interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 7.4 interrupt pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 7.5 dma interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7.5.1 dma interrupt servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7.6 mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7.7 doorbells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 8. error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 8.2 pb interface errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 8.3 pci interface errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 8.4 dma errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 9. resets, clocks and power-up options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.1.1 reset pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.2 clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 9.3 power-up options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 9.3.1 multiplexed system pin mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 9.3.2 configuration slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 9.3.3 assertion of p1_req64# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10. endian mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 10.2 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
contents 6 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 10.3 processor bus and powerspan ii register transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 10.4 processor bus and pci transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 10.4.1 big-endian mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 10.4.2 little-endian mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 10.4.3 powerpc little-endian mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 10.4.4 true little-endian mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11. signals and pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 11.1 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11.1.1 signal types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11.1.2 processor bus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 11.1.3 pci-1 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 11.1.4 pci-2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 11.1.5 miscellaneous signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 11.1.6 test signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 11.2 dual pci powerspan ii pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 11.2.1 dual pci powerspan ii 480 hsbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 11.2.2 480 hsbga pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 11.2.3 dual pci powerspan ii 504 hsbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 11.2.4 504 hsbga pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 11.3 single pci powerspan ii pin information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 11.3.1 single pci powerspan ii 420 hsbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 11.3.2 420 hsbga pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 11.3.3 single pci powerspan ii 484 hsbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 12. register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 12.1 register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 12.1.1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 12.1.2 access from pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 12.1.3 access from the processor bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 12.1.4 access from multiple interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 12.2 register reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 12.3 configuration and iack cycle generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 12.3.1 from pci-to-pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 12.3.2 from the processor bus to pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 12.4 bit ordering and endian ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 12.5 register descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 13. electrical and signal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381 13.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 13.1.1 pci electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 13.1.2 non-pci electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 13.2 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 13.3 operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 13.3.1 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 13.3.2 handling and storage specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com contents 7 13.3.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 14. package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 14.1 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 14.1.1 single pci powerspan ii 420 hsbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 14.1.2 dual pci powerspan ii 480 hsbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 14.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 14.2.1 single pci 420 hsbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 14.2.2 dual pci 480 hsbga package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 15. ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 15.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 15.2 single pci powerspan ii timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 15.3 dual pci powerspan ii timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 15.4 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 16. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 16.1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 a. hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 a.2 recommended bootstrap diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 a.3 pll external decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 a.3.1 backwards compatible pll decoupling for migrating powerspan ii designs . . . . . . . . . . . . . . . . . 418 a.3.2 powerspan ii external pll decoupling for new designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 b. typical applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 b.2 powerquicc ii and powerspan ii applicat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 b.2.1 direct connect support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 b.2.2 compactpci adapter card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 b.2.3 compactpci host card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 b.3 winpath and powerspan ii applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 index 433
contents 8 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com
powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 9 list of figures figure 1: powerspan ii block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 2: typical powerspan ii application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 3: non-transparent pci-to-pci in compactpci application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 4: concurrent read process with powerspan ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 5: reads with conventional fifo-based bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 6: concurrent read waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 7: powerspan ii in a compactpci adapter card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 8: hot swap insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 9: hot swap extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 10: powerspan ii i2o message passing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 11: powerspan ii i2o pull capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 12: powerspan ii i2o outbound capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 13: pb master interface burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 14: pb master interface burst write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 15: pb master interface single cycle read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 16: pb master interface single cycle write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 17: direct mode dma transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 18: dma command packet linked-list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 19: sequence of operations in a linked-list transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 20: assignment of additional bus requesters with pci arbite rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 21: arbitration algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 22: powerspan ii power-up waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 23: powerspan ii configuration slave mode timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 24: 480 hsbga. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 25: 504 hsbga. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 figure 26: 420 hsbga. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 figure 27: 484 pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 figure 28: 420 hsbga. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 figure 29: 480 hsbga. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 figure 30: power-up reset: compactpci adapter scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 figure 31: power-up options: multiplexed system pin approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 figure 32: power-up options: configuration slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 figure 33: clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 figure 34: pci timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 figure 35: pci miscellaneous timing; compact pci adapter scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 figure 36: p1_req64_ assertion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 figure 37: processor bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 figure 38: interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 figure 39: i2c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 figure 40: bootstrap diodes for power-up sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 figure 41: pll power filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 figure 42: pll decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
list of figures 10 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 43: powerspan ii in multi-processor 60x system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 figure 44: powerspan ii in compactpci peripheral slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 figure 45: powerspan ii in compactpci system slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 11 list of tables table 1: powerspan ii applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 2: powerspan ii functional enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 3: signals involved in pci data width determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 4: command encoding for transaction type?powerspan ii as pci target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 5: programming model for pci target image control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 6: powerspan ii pci target read watermarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 7: command encoding for transaction type (powerspan ii as pci master) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 8: pb writes and their corresponding pci writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 9: powerspan ii pci master read commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 10: powerspan ii i20 target image map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 11: programming model for pb slave image control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 12: recommended memory/cache attribute settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 13: powerspan ii pb slave transfer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 14: translation address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 15: powerspan ii pb address parity assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 16: powerspan ii pb transfer sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 17: powerspan ii processor bus single beat data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 18: read amount settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 19: powerspan ii pb data parity assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 20: default powerspan ii pb master transfer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 21: powerspan ii pb address parity assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 22: powerspan ii pb transfer sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 23: 64-bit pb data bus byte lane definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 24: powerspan ii processor bus single beat data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 25: powerspan ii pb data parity assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 26: dma register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 27: programming model for dma general control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 28: default powerspan ii pb master transfer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 29: programming model for the command packet contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 30: dma channel interrupt sources and enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 31: power-up eeprom load sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 32: mx_en default state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 33: interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 34: register description for interrupt status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 35: register description for interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 36: register description for interrupt enable register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 37: register description for interrupt enable register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 38: mapping definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 39: dma channel interrupt sources and enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 40: pb interface errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 41: pci interface errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 42: powerspan ii reset pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
list of tables 12 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com table 43: reset direction control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 44: powerspan ii reset response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 45: powerspan ii power-up options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 46: pci byte lane definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 47: 64-bit pb data bus byte lane definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 48: powerspan ii big-endian pb register accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 49: processor bus address munging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 50: powerspan ii powerpc little-endian pb register access es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 51: powerspan ii big-endian mode byte lane mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 52: powerspan ii little-endian mode byte lane mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 53: powerspan ii true little-endian byte lane mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 54: signal type definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 55: processor bus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 56: pci-1 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 57: pci-2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 58: miscellaneous signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 59: test signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 60: package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 61: package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 62: package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 table 63: package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 table 64: powerspan ii register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 table 65: abbreviations used in register descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 table 66: read amount versus read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 table 67: block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 table 68: setting for mode and mem_io bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 table 69: read amount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 table 70: arbitration pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 table 71: pci-2 ad[31:11] lines asserted during configuration t ype 0 cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 table 72: parked pci master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 table 73: block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 table 74: setting for mode and mem_io bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 table 75: read amount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 table 76: translation address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 table 77: pci ad[31:11] lines asserted during configuration type 0 cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 table 78: mx_en default state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 table 79: parked processor bus master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 table 80: arbitration pin mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 table 81: mapping definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 table 82: block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 table 83: read amount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 table 84: host outbound post list size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 table 85: i2o fifo sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 table 86: hbga electrical characteristics (non-pci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 table 87: single pci powerspan ii power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com list of tables 13 table 88: dual pci powerspan ii power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 table 89: operating and storage conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 table 90: absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 table 91: package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 table 92: package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 table 93: thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 table 94: 420 hsbga package performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 table 95: thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 table 96: 480 pbga package performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 table 97: reset, and clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 table 98: pci 33 mhz timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 table 99: pci 66 mhz timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 table 100: pb timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 table 101: miscellaneous timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 table 102: reset, and clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 table 103: pci 33 mhz timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 table 104: pci 66 mhz timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 table 105: pb timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 table 106: miscellaneous timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 table 107: standard ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
list of tables 14 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com
15 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com about this document this section discusses the following topics: ? ?scope? on page 15 ? ?document conven tions? on page 15 ? ?revision history? on page 16 scope the powerspan ii user manual discusses the featur es, configuration requ irements, and design architecture of the powerspan ii. document conventions this document uses th e following conventions. non-differential signal notation non-differential signals are either ac tive-low or active-high. an active-l ow signal has an active state of logic 0 (or the lower voltage leve l), and is denoted by a lowercase ?_? or ?#? for pci signals. an active-high signal has an active state of logic 1 (or the higher voltage level), and is not denoted by a special character. the following table illustrates the non-differ ential signal naming convention. object size notation ?a byte is an 8-bit object. ?a word is a 16-bit object. ?a doubleword (dword) is a 32-bit object. state single-line signal multi-line signal active low name_ name[3]_ active low name# name[3]# active high name name[3]
about this document 16 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com numeric notation ? hexadecimal numbers are denoted by the prefix 0x (for example, 0x04). ? binary numbers are denoted by the prefix 0b (for example, 0b010). ? registers that have multiple iterations ar e denoted by {x..y} in their names; where x is first register and address, and y is the last register and address. for example, reg{0..1} in dicates there are two versions of the register at diff erent addresses: reg0 and reg1. symbols document status information ? advance ? contains information that is subject to change, and is available once prototypes are released to customers. ? preliminary ? contains information about a product that is near production-r eady, and is revised as required. ? formal ? contains information about a final, cu stomer-ready product, and is available once the product is released to production. revision history 80a1010_ma001_09, form al, november 2009 this document was rebranded as idt. it does not include any technical changes. 80a1010_ma001_08, form al, march 2007 the formatting of this document has been changed and technical edits have occurred throughout the document. 80a1010_ma001_07, form al, february 2003 the dual pci powerspan ii has reached production status. this manual represents the production information for the dual pci powerspan ii. tip this symbol indicates a basic design conc ept or information considered helpful. this symbol indicates important conf iguration informatio n or suggestions. this symbol indicates procedures or operating levels that may re sult in misuse or damage to the device.
about this document 17 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 80a1010_ma001_06, form al, december 2002 the single pci powerspan ii has reached production status. this manual represents the production information for the single pci powerspan ii.
about this document 18 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com
19 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 1. functional overview this chapter describes the powe rspan ii?s architecture. the fo llowing topics are discussed: ? ?pci interface? on page 24 ? ?processor bus interface? on page 26 ? ?dma controller? on page 26 ? ?i2c / eeprom? on page 27 ? ?concurrent reads? on page 27 1.1 overview the idt powerspantm ii is a multi-port pci bus switch that bridges pci to the powerquicc ii (mpc8260), powerpctm 7xx, and the wintegra winp athtm processors. powers pan ii is available in either a single pci or dual pci vari ant. powerspan ii defines a new leve l of pci bus switch flexibility. the integrated, non-transparent pci- to-pci bridge in the dual pci po werspan ii provides a significant opportunity for designers to reduce component count and increase overall system performance. powerspan ii offers a flexible package design. the de sign is available in both the original powerspan package dimensions and newly designed, smaller packages. the high level of performance and flexibility of powerspan ii is made possible through switched pci - unique to powerspan ii. switched pci uses a switching fabric to en able data streams to pass from port-to-port across the multi-ported powerspan ii without collision. this improves the burst performance and decreases latency on the pci a nd processor buses ? a ke y element in enabling increased i/o performance.
1. functional overview 20 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 1: powerspan ii block diagram 1.1.1 powerspan ii features powerspan ii has the following features: 1.1.1.1 processor support ? direct connect interface for embedded processors: ? motorola: powerquicc ii (mpc825x, mp c826x, mpc827x, mpc8280), powerpc 7xx (mpc74x,mpc75x), powerpc 7400 ? ibm: powerpc 740, powerpc 750 ? wintegra: winpath tm ? 25 mhz-to-100 mhz bus frequency ? programmable endian conversion ? powerquicc ii configuration slave support for power-up options ieee1149.1 boundary scan up to 7 external bus masters up to 8 slave devices hot swap friendly - programmable on pci-1 or pci-2 up to 7 external bus masters up to 3 external bus masters 32-bit address/64-bit data 100 mhz processor bus powerpc processor bus interface pb arbiter pci-1 arbiter pci-2 arbiter pci-1 interface pci-2 interface (optional interface) jtag hot swap controller dma registers 32-bit address and data 66 mhz pci bus 32-bit address / 64-bit data 66 mhz pci bus switching fabric pci-to-processor posted writes concurrent delayed reads concurrent dma reads/writes processor-to-pci posted writes concurrent delayed reads concurrent dma reads/writes pci-to-pci posted writes concurrent reads concurrent dma reads/writes interrupts 80a1010_bk001_03 i 2 c
1. functional overview 21 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com ? eight programmable memory maps to pci from the processor ? processor bus arbiter with support for three requesters 1.1.1.2 pci support ? dual pci powerspan ii: ? one 32-bit or 64-bit pci interface ? one 32-bit interface ? 66 mhz operation ? single pci powerspan ii: ? one 32-bit or 64-bit pci interface ? 66 mhz operation ? integrated, non-transparent pci-to-pci bridge in the dual pci powerspan ii ? pci arbiters on each pci interface ? compactpci hot swap friendly ? pci 2.2 specification compliant 1.1.1.3 packaging options ? single pci powerspan ii (ca91l8260b) ? 64-bit/66mhz ? 420 hsbga: 1.27mm ball pitch, 35mm body size ? 484 pbga: 1.0mm ball pitch, 23mm body size ? dual pci powerspan ii (ca91l8200b) ? 32-bit/66mhz and 64-bit/66mhz ? 480 hsbga: 1.27mm ball pitch, 37.5mm body size ? 504 hsbga: 1.0mm ball pitch, 27mm body size 1.1.2 powerspan ii benefits powerspan ii offers the follow ing benefits to designers: ? smaller packages reduce board ar ea required for system design. ? integrated pci bus, processor bus arbiters decrease individual compon ent count on boards. ? flexible pci interfaces enable powerspan ii to meet many different application requirements. ? integrated, non-transparent pci-to-pci bridge connects traffic between the two pci interfaces. this decreases individual component count and simplifies conven tional compactpci board architecture. ? supports reads from multiple i/o devices in pa rallel, non-blocking str eams which decreases bus latency.
1. functional overview 22 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 1.1.3 typical applications idt understands vendors? needs to increase performance throughout today?s communications networks. from premise equipment to local carrier gear to high-end switches, designer?s need to deliver ever-faster traffic through the same or smaller footprint at a reduced cost. idt system interconnect helps in that effort by providing features and benefits across all areas of the network. powerspan ii helps designers wo rking on infrastructure equipment in the following areas: powerspan ii is a very flexible device. the following diagram shows a typical powerpc system architecture using powerquicc ii and the dual pci powerspan ii. figure 2: typical powerspan ii application table 1: powerspan ii applications lan/wan remote/local access wireless exchange carrier switching equipment adsl concentrators third generation (3g) base stations ethernet switches voip gateways mpeg 2 encoders vpn equipment powerspan ii pmc connectors pci-1 32-bit address/64-bit data 66 mhz 32-bit address/32-bit data 66 mhz pci-2 (optional) processor bus 32-bit address/64-bit data 66 mhz/100 mhz (ppc 740/750) memory controller mpc8260 pci bus 80a1010_ta001_02
1. functional overview 23 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 1.1.4 powerspan ii and powe rspan differences summary the following table summarizes the main powerspan ii programmable features that were unavailable in the powerspan device. all functi onal enhancements are programmable in order to make sure that all original powerspan functiona lity can be exercised. table 2: powerspan ii functional enhancements functional enhanc ement descriptions see packaging change packaging has been changed from hpbga packages to hsbga packages. four variants are available for powerspan ii: two variants for the single pci powerspan ii and two variants for the dual pci powerspan ii. both the single and dual pci powerspan ii have packages, signals, and pins that are backwards compatible with the original powerspan device. ?electrical and signal characteristics? on page 381 and ?package information? on page 387 new revision id powerspan ii has a new id. ?register descriptions? on page 235 read implementation powerspan ii supports 4 byte transactions. ?pci interface? on page 31 , ?processor bus interface? on page 83 , and ?register descriptions? on page 235 true little-endian mode a new endian mode was developed for powerspan ii ?endian mapping? on page 177 , and ?register descriptions? on page 235 base address implementation powerspan ii supports a pci base address of 0x00000. ?register descriptions? on page 235 maximum retry counter modification the maximum retry counter is programmable in powerspan ii ?register descriptions? on page 235 arbitration timing for masters powerspan ii measures the length of time it takes a master to respond to the gnt# signal. ?arbitration? on page 137 and ?register descriptions? on page 235 powerpc 7400 transaction support powerspan ii has been designed to support specific powerpc 7400 misaligned transactions. ?processor bus interface? on page 83 and ?register descriptions? on page 235 delay sampling of transaction start signal the powerspan ii pb arbiter can be programmed to sample requests two clocks after the pb_ts_ signal is asserted. ?arbitration? on page 137 and ?register descriptions? on page 235
1. functional overview 24 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 1.2 pci interface powerspan ii is available as a si ngle pci powerspan ii or dual pci powerspan ii. a 64-bit pci interface is available on both variants; the du al pci powerspan ii has a 32-bit pci interface in addition to the 64-bit pci interface. in both case s, the pci interfaces on the powerspan ii support 66mhz operation and are asynchronous to the other interfaces on the device. the pci interfaces are pci 2.2 specification compliant. 1.2.1 pci-to-pci bridge the dual pci powerspan ii is a pci-to-pci bridge. it connects traffic between the two pci interfaces. this pci-to-pci bridging function is ?non-transparent?. in a non-tr ansparent bridge one pci bus is hidden from system bios running in the other pc i domain. memory and i/o transfers pass freely between the pci interfaces, but conf iguration accesses are filtered. the application is shown in figure 3 . programmable dma block size powerspan ii enables programmable dma block sizes. ?dma? on page 113 and ?register descriptions? on page 235 pb arbiter qualifies bus grants the powerspan ii pb arbiter can be programmed to qualify data bus grants before issuing data bus grants. ?arbitration? on page 137 and ?register descriptions? on page 235 target fast back to back capable (tfbbc) the default setting of this bit was changed to 0 in powerspan ii; the device does not support fast back-to-back transactions. ?register descriptions? on page 235 table 2: powerspan ii functional enhancements functional enhanc ement descriptions see
1. functional overview 25 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 3: non-transparent pci-to-pci in compactpci application because of the non-transparent pci-to-pci bridging , the host processor on the compactpci adapter card acts as local host without the local pci devices being configured by the compactpc i system host. 1.2.2 primary pci interface the powerspan ii provides extra functionality fo r one of the pci interfaces. the pci interface assigned extra functionality must be specified as primary pci in terface through a power-up option. the primary pci inte rface functions are: ? compactpci hot swap friendly support ? i 2 o 2.0 specification compliant messaging ? vital product data support. this extra functionality is available for th e single pci powerspan ii and the dual pci powerspan ii. host processor as local controller one or more local i/o controllers (for example, gigabit ethernet, ieee 1394) to compactpci back-plane mem host dual pci powerspan
1. functional overview 26 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 1.2.3 pci host bridge powerspan ii is designed for host bridge applicat ions. the powerpc processo r generates configuration cycles on the pci bus in the same way as that found in conventional pci host br idges. in addition, with concurrent reads and low device latency, the pc i target interface on powerspan ii is specifically designed to allow low latency acces s to host packet memory for i/o controllers on either of the pci buses. 1.2.4 pci bus arbitration each pci interface has an integrated pci bus arbiter. each arbiter supports four external bus requesters. an additional three bus requesters can be assigned between the two pci arbiters. the pci arbiters implement a fair ness algorithm, two roun d robin priority levels and flexible bus parking options. 1.3 processor bus interface the powerspan ii provides a direct-connect 64-b it interface to the powerquicc ii (mpc8260), mpc7xx, powerpc tm 7xx, and the wintegra winpath tm processors. the direct -connect support for these interfaces has been extensiv ely verified during product devel opment with processor functional models as well as with a hardware emulation methodology. this verification ensures any potential interface issues are identified and resolved by idt before powerspan ii customers begin to design their own systems. powerspan ii supports processor (60x) bus extended cycles on the processor interface. extended cycle support means more flexible bursting and more efficient use of th e processor bandwidth. 1.3.1 address decoding instead of consuming chip selects from the processor, powerspan ii performs its own address decoding for up to eight memory (slave) imag es to the pci bus from the proces sor bus. this allows a flexible mapping of processor transact ions to pci cycle types. 1.3.2 processor bus arbitration the processor interface has an integr ated bus arbiter. the processor interface supports three external bus masters for applications invol ving multiple processors . the processor bus ar biter implements two levels of priority, where devices programmed into a specific priority level operate in a round robin fashion in that level. 1.4 dma controller powerspan ii provides four indepe ndent, bidirectional dma channels . each dma channel is capable of linked-list or dire ct mode transfers. each dma channel transfers data from any-port to any-port. for example, from pci-1 to pci-2, processor bus to pci-1, or processor bus and processor bus. high throughput data transfer is coupled by flexible endian mapping and a range of stat us bits mappable to external interrupts.
1. functional overview 27 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 1.5 i 2 c / eeprom 1.5.1 eeprom powerspan ii registers can be programmed by data in an eeprom at system reset. this enables board designers to set unique identifi ers for their cards on the pci bus at reset, and set various image parameters and addresses. conf iguring powerspan ii with the eeprom allows powerspan ii to boot-up as a plug and play compatible device. po werspan ii supports reads from, and writes to, the eeprom. 1.5.2 i 2 c powerspan ii has a master only i 2 c bus compatible interface whic h supports up to eight i 2 c slave devices. this interface is used by powerspan ii for the initialization of registers and for reading and writing pci vital product data (vpd). powerspan ii also provides a mechanism to perform ma ster read and write operations to eeproms or other i 2 c compatible slave devices. 1.6 concurrent reads powerspan ii?s switched pci architecture enables concurrent reads through a single channel. this ability greatly reduces read la tency, which is often the limit ing factor in pci performance. 1.6.1 powerspan ii?s concurrent read solution with powerspan ii?s concurrent reads, read reques ts are accepted even while the current read is in progress. figure 4 illustrates the concu rrent read process wi th the powerspan ii.
1. functional overview 28 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 4: concurrent read process with powerspan ii when master 2 makes its first read request in step 2, it is retried but informat ion about the read request is latched and initiates a read on the other bus. th is occurs even though a r ead is in progress for master 1. powerspan ii can simultaneously support two reads to the processor bus and two reads to the pci bus. 1.6.1.1 conventional reads and retries in conventional fifo-based bridge architectures, bu s masters must take turn s for read opportunities and incur multiple retries while waiting. figure illustrates the read proces s for subsequent reads where retries are incurred while a pending read is completed. master 1: makes a read request and is retried. read 1 request read 1 read request master 2: makes an initial read request and is retried. read 2 master 1: takes the read data master 2: takes read data read request master 1: makes request 1. 2. 3. 4.
1. functional overview 29 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 5: reads with conven tional fifo-based bridges when master 2 is retried in step 2, no information is latched about the read request. when master 2 returns for a subsequent read request in step 4, it is treated by the bridge as the first read request. 1.6.2 powerspan ii?s concu rrent read applications 1.6.2.1 pci host bridge in a pci host bridge application, all of the pci masters ? for example, i/o controllers ? potentially receive only one retry before receiving read data. ev en with another read pending, when the pci target interface of the pci host device receives a read reque st, it latches the inform ation and begins another burst read prefetch on the proces sor bus. the pci host bridge latc hes the addresses and delivers the data to each master using separa te, dedicated buffering. this appr oach greatly reduces the overall system latency and allows for a more scalable i/o subsystem. master 1: makes a read request. read 1 request 1. master 1: takes the read data. 2. read 2 request master 2: makes a read request and is retried. master 2: makes another read request. 4. read 2 read 1 master 1: makes another request and is retried. 3. master 2: takes the read data. 6. 5.
1. functional overview 30 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 1.6.2.2 adapter card in an adapter card application, the read latenc y problem is a mirror image of a pci host bridge application. in an adapter card, th e powerquicc ii serial ports (fccs) may be expected to transfer bit streams through the powerquicc ii/pci to host memory across the pci bus. in this case, there can be eight separate fccs potentially contending for the processor slave interface in the pci bridge ? assuming there are two powerquicc iis on the local bus. this architec ture adds considerable latencies to read transactions because of f ccs attempting reads to host memory across the pci bus. ideally, each fcc would have a dedicated channe l to the pci bus so they do not have to share resources. powerspan ii supports this ideal situation through its concurrent reads in a flexible switching architecture. the pci bridge latches information abou t the local read as it receives the read request even with reads pending. the fccs can now receive transmit data from system host memory with far lower latencies.
31 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2. pci interface peripheral component interconnect (pci) is a bus protocol that defines how devices communicate on a peripheral bus and with a host processor. if a devi ce is referred to as pci compliant it must be compliant with the pci local bus specification (revision 2.2) . a pci bus supports frequencies up to 66 mhz, and 32-bit or 64-bit transfers. this chapter describes the pci interface of the du al pci powerspan ii. the following topics are discussed: ? ?overview? on page 31 ? ?pci target interface? on page 37 ? ?pci master interface? on page 46 ? ?compactpci hot swap si licon support? on page 53 ? ?vital product data? on page 60 ? ?i2o shell interface? on page 62 2.1 overview this chapter describes the functionality of the dual pci powerspan ii. the single pci powerspan ii is identified when its fu nctionality or settings differ from the dual pci powerspan ii. the single pci powerspan ii and the dual pci po werspan ii have different characteristics. the features of each device are shown in the following list. ? dual pci powerspan ii: ? one 32-bit or 64-bit pci interface ? one 32-bit interface ? 66 mhz operation ? single pci powerspan ii: ? one 32-bit or 64-bit pci interface ? 66 mhz operation 2.1.1 primary pci the dual pci powerspan ii has two pci interfaces: the pci-1 interface and the pci-2 interface. pci-1 interface is 32-bit or 64-bit capable, while the pci-2 interface is 32-bit. both pci interfaces have 66 mhz capability.
2. pci interface 32 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com there are two settings available for the dual pci powerspan ii: primary pci interface and secondary pci interface. the primary pci interfa ce adds extra functionality to the pci interface that is designated as the primary pci interface. the secondary pci interface has no extra functionality. the following features are associated with the primary pci interface: ? compactpci hot swap support (see ?compactpci hot swap si licon support? on page 53 ) ? vital product data (see ?vital product data? on page 60 ) ?i 2 o shell interface (see ?i2o shell interface? on page 62 ) either the pci-1 interface (64-bit) or the pci-2 interface (32-bit) can be configured as the primary interface. the selected pci interface is assigned as the primary pci interface through the primary pci select (pwrup_pri_pci) power-up option (see ?resets, clocks and power-up options? on page 167 for more information). primary pc i functionality is shown in th e value of the primary pci bus (pri_pci) bit in the ?reset control and status register? on page 324 . the pri_pci is a status bit and only shows which bus is primary. it does not enab le a bus as the primary pci interface. the primary pci interface is enabled with a power-up option (see 9. ?resets, clocks and power-up options? on page 167 ). 2.1.1.1 clock frequencies each of the pci interfaces, pci-1 and pci-2, run at frequencies from 25 mhz to 66 mhz. the dev66 bit in the ?pci-1 control and status register.? on page 251 indicates that powerspan ii is a 66 mhz-capable device. the speed of these buses is determin ed through a power-up option (see ?clocks? on page 170 and ?power-up options? on page 171 ) using the corresponding p1_m66en pins. both pci interfaces run asynchronously to one an other, and asynchronously to the processor bus interface. 2.1.2 pci data width the pci-1 interface is a 64-bit data interface that su pports 32-bit addressing. the pci-2 interface is a 32-bit data interface that supports 32-bit addressing. 2.1.2.1 powerspan ii in non-hot swap and pci host applications the pci-1 interface can be programmed to assert p1_r eq64# to indicate the da ta width of the pci-1 bus at reset. this feature is controlled by the pwrup_p1_r64_en power-up option (see ?power-up options? on page 171 ) and minimizes required external logi c. a logic low applied to p1_64en# enables this feature. powerspan ii drives p1_r eq64# when pwrup_p1_r64_en is selected and p1_64en# is set to 0. the primary pci bus (pri_pci) bit in the ?reset control and status register? on page 324 is always 0 in the single pci powerspan ii.
2. pci interface 33 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com when p1_64en# is at a logic low, and pwrup_p1_r 64_en is selected, p1_req64# is asserted low during reset. the status of pwrup_p1_r64_en is reflected in the p1_r64_en bit in the ?reset control and status register? on page 324 . 2.1.2.2 powerspan ii in non-hot swap and pci peripheral applications the pci-1 interface supports the following mechanisms for determining the width of the pci-1 datapath: ? sampling p1_req64# at the negation of p1_rst# ? logic level on p1_64en# in non-hot swap applications, the p1_64en# signal must be pulled high in order to enable sampling of p1_req64# to determine the width of the data path . the result of the sampling of p1_req64# is or?d with the logic level on p1_64en# to determine data path width (see table 3 ). 2.1.2.3 powerspan ii in hot swap applications in hot swap applications the p1_64en# signal is the only signal sampled to indicate the pci data width. the following scenarios can be used for determining th e proper implementation of the p1_req64# and p1_64en# signals: ? pci bus is currently a 32-bit slot and the ho t swap board is 64-bit capable. in this case, p1_req64# is pulled up in the slot and p1_64en# is open and the card will initialize in 32-bit mode. ? pci bus is currently a 32-bit slot and the ho t swap board is 32-bit capable. in this case, p1_req64# is not sampled and p1_64en# does no t exist on the board so initialization would be 32-bit mode. this feature must only be used in system s where powerspan ii controls both p1_req64# and p1_rst#. in this scenario, powerspan ii is the central resource in the system and can ensure that timing parameters are satisfied. table 3: signals involved in pci data width determination signal result p1_req64# p1_64en# 0 0 64-bit bus 1 0 64-bit bus 0 1 64-bit bus 1 1 32-bit bus
2. pci interface 34 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com ? pci bus is currently a 64-bit slot and the ho t swap board is 64-bit capable. in this case, p1_req64# could be anything but p1_64en# is gnd and the card will initialize in 64-bit mode. ? pci bus is currently a 64-bit slot and the ho t swap board is 32-bit capable. in this case, p1_req64# is not sampled and p1_64en# does no t exist on the board so initialization would be 32-bit mode. 2.1.2.4 powerspan ii drives pci 64-bit extension signal in 32-bit environment when powerspan ii's 64-bit pci in terface is programmed to operate in 32-bit mode, the 64-bit extension pci bus signals can be left open. powerspan ii actively drives the following the input signals: ? driven low ? p1_adb[63:32]# ? p1_cbe[7:4]# ?p1_req64# ? p1_ack64# ?p1_par64# ?p1_par64# ? p1_req64# ? p1_ack64# this insures the signals do not oscill ate and that there is not a signif icant power drain through the input buffer. 2.1.3 pci interface descriptions the powerspan ii pci interfaces are described in terms of its pci master and pci target functions. this description is largely independen t of pci-1 versus pci-2, or th e assignment of the primary pci interface functions. exceptions to these rules are noted as required. 2.1.4 transaction ordering powerspan ii implements a set of ordering rules for tr ansactions initiated by master(s) connected to pci interface px, that are destined for targets and/or slaves connected to pci interface py. cross-references to pc i registers are shown as pci-1 whenever the cross-references apply equally to pci-1 or pci-2 registers. transactions initiated by mast er(s) connected to pci inte rface px, but with different powerspan ii destination interfaces, are in dependent from an ordering perspective. transactions initiated by powerspan ii dma a nd powerspan ii generated interrupt events have no ordering relationship to externally init iated transactions processed by powerspan ii.
2. pci interface 35 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.1.4.1 transactions between px and py powerspan ii implements the followi ng transaction ordering rules fo r transactions flowing between pci interface px and pci interface py: ? the order in which delayed read requests are la tched on the source bus, and posted memory write transactions are presented on the source bus, is th e order in which they appear on the destination bus. ? writes flowing from px to py have no ordering relationship to writes flowing from py to px. ? the acceptance of a posted write as a target or slave is not contingent on the completion of a transaction by the master of the same interface. powerspan ii master and target/slave modules are independent. 2.1.4.2 transactions between the pb interface and the pci interfaces when there are transactions to the pb interface fro m both pci-1 and pci-2, there is a possibility that a transaction from pci-2 can be que ued ahead of a transaction from pci-. this is caused by the fact there is no transaction ordering between the two independent pci interfaces. for example, if transactions to the pb interface arrive in the following order from pci-1 and pci-2: ? pci-1 write 1 ? pci-2 write 1 ? pci-2 write 2 ? pci-1 write 2 the transactions can be completed to the pb interfa ce in the following order even though pci-2 write 2 entered powerspan ii before pci-1 write 2: ? pci-1 write 1 ? pci-2 write 1 ? pci-1 write 2 ? pci-2 write 2 this is caused by the fact that pc i-1 to pb interface transactions and pci-2 to pb interface transactions arbitrate in a round robin fashion. when a powers pan ii decision is required on whether to service a transaction from pci-1 or pci-2, writ es are available at both even tho ugh at one point a write is only available from pci-2. 2.1.4.3 dma transactions dma transactions and regular write/read transactions arbitrate for the use of a master interface in a round robin scheme. there are no sp ecial priorities for dma transactions and regular write/read transactions.
2. pci interface 36 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com writes and reads from one source are queued and arbi trated for the use of the master interface with dma in a round robin design. a dm a transaction can be given a lowe r priority by programming the dma channel off counter (off) bit in the ?dma x general control and status register? on page 314 . the off bit provides programmable control over the amount of source bus traffic generated by the dma channel. the channel in terleaves source bus transfers with a period of idle processor bus clocks where no source bus requests are genera ted. when source and de stination interfaces are different, 256 bytes of source bus traffic occurs before the idle period. if source and destination interfaces are the same, 64 bytes of source bus traffi c occur before the idle period. this helps prevent powerspan ii from interfering with processor bus instruction fetches. all transactions (writes/reads/dma) from two source interfaces arbitrate in a round robin scheme on a per interface basis. refer to ?transactions between the pb in terface and the pci interfaces? on page 35 for more information. 2.1.4.4 pci transaction ordering rules the pci 2.2 specification outlines transaction ordering rules for pci transactions. powerspan ii does not comply with the following pci transaction ordering rules: ? powerspan ii only completes the writes that are de stined for the same bus as the initiated read when it is processing a read re quest. it does not complete writ es in both directions before processing a read request. powerspan ii do es not prioritize writes over reads. ? powerspan ii does not allow posted memory writes to pass delayed read requests. this implies that deadlock conditions may occur when the custom er uses bridges that do not support delayed transactions. deadlock conditions are broken by the powerspan ii maximum retry counter.
2. pci interface 37 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.2 pci target interface powerspan ii participates in a tran saction as a pci target when a pci master initiates one of the following actions: ? attempts to access the alternate pci interface ? attempts to access processor bus memory ? accesses powerspan ii registers this chapter describes only the first two conditions listed above. transactions targeted for the powerspan ii?s 4 kbytes of device control and status registers are discussed in ?register access? on page 235 . the operation of the pci target is described by divi ding the pci transaction into the following phases: ? address phase: this section discu sses the decoding of pci accesses. ? data phase: this sect ion describes control of burst le ngth and byte lane management. ? terminations: this section describes the terminatio ns supported by the powerspan ii, how they are mapped from the destination port to the pci target, and exception handling. 2.2.1 address phase the address phase deals with the decoding of pci accesses. 2.2.1.1 transaction decoding transaction decoding on the pci ta rget operates in both normal decode mode and master-based decode mode. only memory and co nfiguration cycles are decoded. i/o cycles are not decoded. during normal decode mode, a pci device monitors the px_ad and px_c/be# lines to decode an access to some programmed pci physical address range ? through positive decoding. a pci target image is defined as the range of pci phy sical address space to deco de a pci transaction. a pci target image location and size is controll ed using a base address field and in the ?pci target base address register? on page 259 , and a block size field in the ?pci-1 target image x control register? on page 268 . normal address decoding only applies to memory cycles.
2. pci interface 38 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com table 4 illustrates the command encoding for powerspan ii as pci target. the pci target image decodes and claims pci tr ansactions and controls how these incoming pci transactions are mapped to the de stination port on powerspan ii. table 5 describes the programming model for a pci target image control register. table 4: command encoding for transaction type ? powerspan ii as pci target px_c/be#[3:0] transaction type powerspan ii capable 0000 interrupt acknowledge no 0001 special cycle no 0010 i/o read no 0011 i/o write no 0100 reserved n/a 0101 reserved n/a 0110 memory read yes 0111 memory write yes 1000 reserved n/a 1001 reserved n/a 1010 configuration read yes (type 0 only) 1011 configuration write yes (type 0 only) 1100 memory read multiple yes 1101 dual address cycle no 1110 memory read line yes 1111 memory write and invalidate aliased to memory write table 5: programming model for pc i target image control register bits type description default setting img_en r/w enables the pci target image to decode in the specified physical address range of memory space. disabled ta_en r/w enables address translation (see ?pci-1 target image x translation address register? on page 274 ). disabled
2. pci interface 39 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com bar_en r/w enables the pci base address register. when this bit is set, the px_bstx register is r/w and visible to processor bus access and pci memory cycles. when this bit is cleared, the px_bstx register returns only zeros on a read. writes will have no effect on px_bstx when this bit is cleared. enabled or configurable through eeprom bs[3:0] r/w sets the block size of the pci target image. the size of the image is 64kbyte * 2 bs . default value is 0, can be programmed through any port after reset or loaded through eeprom. mode r/w maps the incoming pci transaction to either memory or i/o space on the alternate pci bus. default value is 0 (memory command generation) dest r/w directs the incoming pci transaction to either the processor bus or the alternate pci interface. defaults to processor bus mem_io r/w commands to the corresponding image generates memory read commands on the destination pci bus (py) with the same byte enables latched from the source bus transaction powerspan ii is capable of performing 1,2,3, or 4 byte memory transfers on the pci bus(es). default value is 0 (regular i/o mode) rtt[4:0] r/w a 5-bit value, defined in the processor bus protocol, is generated on the pb_tt lines during a read on the processor bus. defaults to read gbl r/w controls the assertion of the pb_gbl_ cache control signal. asserts pb_gbl_ ci_ r/w controls the assertion of the pb_ci_ cache control signal. asserts pb_ci_ wtt[4:0] r/w a 5-bit value, defined in the processor bus protocol, is generated on the pb_tt lines during a write on the processor bus. defaults to write with flush prkeep r/w enables powerspan ii to keep prefetch read data over subsequent transactions (see ?reads? on page 41 ). disabled end[1:0] r/w sets endian mapping to little-endian, powerpc little-endian, or big-endian (see ?endian mapping? on page 177 ). big-endian is the default mode. table 5: programming model for pc i target image control register bits type description default setting
2. pci interface 40 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com master-based decode the pci target supports master-based decode wh en the powerspan ii pci arbiter is enabled (see ?arbitration? on page 137 ). with master-based decode enabled, a pci target image only claims a transaction decoded for its specified physical address space if it orig inates from a specific pci master. external bus masters are selected for a specific targ et image by setting the co rresponding bits in the ?pci-1 target image x translat ion address register? on page 274 . 2.2.1.2 address translation the address generated on the destin ation port is dependent on the use of address translation in the source target image. for more information, see th e translation address enab le (ta_en) bit in the ?pci-1 target image x control register? on page 268 . when address translation is enabled ? by setting the ta_en bit ? the address generated on th e destination bus is derived from the following three inputs: ? incoming address on the pci target ? block size of the target image bs[3:0] in the ?pci-1 target image x control register? on page 268 ? translation address taddr in the ?pci-1 target image x translation address register? on page 274 when address translation is disabled the address on th e destination bus is the same as the address on the source bus. 2.2.1.3 transaction type mapping a transaction can be mapped to the pb interface or to another pci interface. mra r/w aliases a memory read command to memory read multiple command. this causes powerspan ii to prefetch read data on the destination bus (processor bus or pci) up to the amount programmed in the rd_amt[2:0] field. disabled rd_amt[2:0] r/w controls the prefetch read amount for a memory read when mra is enabled. memory read multiple always causes prefetch up to the value in rd_amt[2:0]. this can be programmed up to a maximum of 128 bytes. 8 bytes is the default prefetch read amount powerspan ii behavior is undefined if more than one overlapping target image claims a transaction. for example, if two target image ha ve the same base address and size, then they must have unique master bits set in the ?pci-1 target image x translation address register? on page 274 . table 5: programming model for pc i target image control register bits type description default setting
2. pci interface 41 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com mapping to the processor interface the pci target image controls the transaction type on the processor bus through the use of the pb read transfer type (rtt[4:0]) and pb writ e transfer type (wtt[4:0]) bits in the ?pci-1 target image x control register? on page 268 . by default, these bit fields assi gn reads as read operations on the processor bus, and assign incoming writes as write with flush on the processor bus. mapping to a pci interface the pci target image determines the address space on the destination pci bus through the use of the image mode (mode) bit in the ?pci-1 target image x control register? on page 268 . by default, incoming pci transactions are ma pped to memory space on the alternate pci interface. setting the mode bit maps incoming pci transactions to i/o space on the alternate pci interface. 2.2.1.4 address parity the pci target image monitors pari ty during the address phase of dec oded transactions. address parity errors are reported on px_serr# when both the parity error re sponse (peresp) and serr enable (serr_en) bits are set in the ?pci-1 control and status register.? on page 251 . assertion of the px_serr# signal can be disabl ed by clearing the serr_en bit. powerspan ii records an error condition in th e event of an address parity error (see ?error handling? on page 157 ). powerspan ii claims the errored transact ion and forwards the transaction to the destination bus. 2.2.2 data phase the data phase deals with control of bur st length and byte lane management. 2.2.2.1 writes powerspan ii accepts single beat or burst transactions in memory spac e. i/o accesses are not decoded. all writes to the pci target are posted writes. burst writes are linear bursts. a target-disconnect is issued if a buffer fills while a burst write is in progress (see ?termination phase? on page 44 ). powerspan ii can manage arbitrary pci byte enable combinations during pci burst writes. 2.2.2.2 reads powerspan ii supports up to four concurrent reads from external pci masters. al l four reads are treated equally and have the same pr efetch capacity, but have indi vidually programmable values. powerspan ii does not support delayed wr ite transactions as described in the pci 2.2 specification .
2. pci interface 42 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com an example of powerspan ii?s concurrent read capability is illustrated in figure 6 . the concurrent reads in the figure are represented by read a and r ead b. in the figure, both read a and read b are retried. once read a is completed on the processor bu s, read b is initiated on the processor bus while the contents of read a are return ed to the pci master. because read b is completed on the processor bus while read a data is returned to the pci bus, re ad latency is significantly reduced with concurrent reads. figure 6: concurrent read waveform see ?concurrent reads? on page 27 for a general discussion of read pipelining in powerspan ii. concurrent read phases the delayed, concurrent reads on the pci target consist of the following phases: 1. delayed read request ? the pci target latches the transaction parameters and issues a retry. 2. delayed read ? the pci target obtains the requested data. the destination bus master retries requested data. 3. delayed read completion ? the master repeats the transaction with the same parameters used for the initial request and data is provided by powerspan ii. read line buffers are allocated on a first come, first serve basis. when an external master makes the initial memory request, the powerspan ii pci target captures the pci address in an available delayed read request latch. this initiates a read on the de stination bus specified by the destination bus (dest) bit in the ?pci-1 target image x control register? on page 268 . prefetch reads all powerspan ii pci target memory reads are considered prefetch able to 8-byte boundaries by default. setting the mem_io bit in the ?pci-1 target image x transl ation address register? on page 274 enables 1,2,3, or 4 byte memory reads on the pci bus and 4 byte reads on the processor bus. when powerspan ii is programmed to support 4 byt e transactions, only 4 byte transactions are supported. burst transactions are not supported while the mem_io bit is set to 1. processor bus pci bus ret-a ret-b ret-a ret-b acc-a completion-a acc-b completion-b ppc-rdb ppc-rda device, arbitration and memory latency arbitration and memory latency single read latency double read latency
2. pci interface 43 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com in order to program powerspan ii to complete 4 byte reads on the pci bus, both the mem_io bit and the mode bit must be set to 1 in the pci x target image x control register. in order to perform a 4-byte read from the pci bus to the processor (60x) bus, the following bits must be programmed: ? mem_io bit set to 1 ? mode bit set to 1 or 0 ? end bit, in the ?pci-1 target image x control register? on page 268 , must not be set to little-endian mode (00). it can be set to po werpc little-endian (01), or big-endian (10). powerspan ii prefetch behavior on the destination bus when claiming memory reads on the originating bus is controlled by the pci me mory read alias (mra ) bit and the prefetch size (rd_amt[2:0]) field in the ?pci-1 target image x control register? on page 268 . if the mra bit is set when powerspan ii claims a memory read, powerspan ii prefetches the amount programmed into the rd_amt[2:0] field ? up to 128 bytes. the memory read line command results in a prefet ch of the value programmed into cache line (cline) bit. when the mra bit is cleared, the ta rget image prefetches 8 bytes when a pci memory read command is decoded. the memory read multiple command results in a prefet ch read of a minimum of 32 bytes or the value programmed into the rd_amt[2:0] field ? independent of the mra bit setting. the powerspan ii pci target read watermarks are defined in table 6 . powerspan ii never prefetches data beyond a 4-k byte address boundary rega rdless of the value programmed in the rd_amt field. this bound ary corresponds to the processor bus memory management page size. when the target image control register is programmed for 4 byte read transactions, requesting 8 byte reads causes undefined results in the system. table 6: powerspan ii pci target read watermarks pci command prefetch amount memory read 8 bytes (default) or 1,2,3, or 4 bytes depending in the setting in the mem_io bit in the ?pci-1 target image x control register? on page 268 memory read line minimum of cline in the ?pci-1 miscellaneous 0 register? on page 255 register memory read multiple minimum of 32 bytes or rd_amt.
2. pci interface 44 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the powerspan ii pci target can be configured to ke ep prefetch data over multiple read accesses for any master that provides the correct address ? by setting the prkeep bit in the ?pci-1 target image x control register? on page 268 . powerspan ii increments its latche d address for the read transaction based on the amount of data removed by the pci mast er during the read transaction. if the pci master returns with an address that matches the incremente d address held by powerspan ii, then powerspan ii provides data already held in the prefetch line buffer. 2.2.2.3 data parity powerspan ii monitors px_par#/px_p ar64# when it accepts data as a pci target during a write. powerspan ii drives px_par#/px_par64# when it provi des data as a pci target during a read. in both cases, the px_par#/px_par64# signal provides ev en parity for px_c/be# [3:0] and px_ad[31:0] ? or px_c/be#[7:4] and px_ad[63:32] for the pci-1 interface in 64-bit mode. the peresp bit in the ?pci-1 control and status register.? on page 251 determines whether or not powerspan ii responds to parity erro rs as a pci target. data parity errors are reported through the assertion of px_perr# when the peresp bit is set. the detected parity e rror (d_pe) bit in the ?pci-1 control and status register.? on page 251 is set when powerspan ii encounters a parity error as a pci target on any transaction. po werspan ii records an error conditio n when a parity error occurs (see ?error handling? on page 157 ). 2.2.3 termination phase this section describes the termina tions supported by the powerspan ii, how they are mapped from the destination port to the pci ta rget, and exception handling. 2.2.3.1 pci target terminations the pci target interface generate s the following terminations: 1. target-disconnect (with data): a termination is requested by the pci target ? by asserting px_stop# and px_trdy# ? when it requires a ne w address phase. target-disconnect means the transaction is terminated after on e or more valid data transfers. the pci target requests a target-d isconnect in the following cases: ? powerspan ii is unable to buffer an incoming wr ite or provide data from a read buffer during a read. ? powerspan ii reaches the 4-kbyt e address boundary on reads an d writes to the processor bus. ? one data phase for powerspan ii register accesses ? one data phase for i 2 o shell accesses ? detection of a transaction with non-linear addressing writes do not invalidate read buffer contents.
2. pci interface 45 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2. target-retry: a termination is requested ? by asserting px_stop# and px_devsel# while px_trdy# is high ? by the pci target because it cannot currently process the transaction. retry means the transaction is terminat ed after the address phase without any data transfer. powerspan ii retries read requests while it fetches data from the destination bus. any attempt by a pci master to complete the memory read transaction is retried by the pci target until at least an 8-byte quantity is available in the line buffer. if a pci mast er does not retry the transaction within 2 15 clocks after a read request has been latched, the delayed read re quest latch and line buffer are de-allocated. this prevents deadlock conditions. 3. target-abort: the pci target requests a terminat ion of a transaction ? by negating px_devsel# and px_trdy# and asserting px_stop# on the same clock edge ? when it cannot respond to the transaction, or during a fatal error. a fatal erro r occurs when: a bus erro r is experienced on the processor bus, the maximum retry count is exceed ed, a target-abort occurs on the alternate pci bus during a read, or a master-abort occurs on the alternate pci bus during a read. although there may be a fatal error for the initiating application, the transaction completes gracefully, ensuring normal pci op eration for other pci resources. powerspan ii sets the signaled target-abort (s_ta) bit in the ?pci-1 control and status register.? on page 251 , and records an error condition in the event of a target-abort (see ?error handling? on page 157 ) error logging and interrupts the powerspan ii pci target records e rrors under the following conditions: ? address parity error ? data parity error on writes ? target-abort see ?error handling? on page 157 and ?interrupt handling? on page 145 for a full description of error logging support and associated interrupt mapping options.
2. pci interface 46 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.3 pci master interface in order for powerspan ii to be a pci master in a transaction the bus master (bm) bit, in the ?pci-1 control and status register.? on page 251 , must be set. with this bit set, powerspan ii is pci master in a transaction in the following instances: ? servicing a request by: ? the processor bus: powerspan ii is accessed as a pb slave ? the alternate pci interface: powerspan ii is accessed as a pci target ? processing a transfer by one of th e four powerspan ii dma channels ? generating a configuration or iack cycle because of a powerspan ii register access this section discusses only the first three condition s listed above. configuration and iack cycles are discussed in ?configuration and iack cycle generation? on page 246 . the operation of the pci master is described by dividing the pci mast er transaction into the following phases: ? arbitration phase: this section describes how powerspan ii reques ts the pci bus and its response to bus parking. ? address phase: this section discusses the gene ration of the pci address and command encoding. ? data phase: this se ction describes control of burst length. ? terminations: this section explains the terminations supported by powerspan ii, how they are mapped to the source port (processor interface or the alternate pci interface), and exception handling. powerspan ii cannot be both master and target on a pci bus at the same time.
2. pci interface 47 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.3.1 arbitration phase: arbi tration for the pci bus powerspan ii issues a bus request on the pci bus wh en it requires access to the pci bus. when the powerspan ii pci arbiter is active, this request is in ternal. when it is not en abled the request appears externally (see ?pci interface arbitration? on page 137 for more information). the internal powerspan ii pci arbite r parks the bus on a pci master by asserting px_gnt# to the pci master. bus parking improves the performance of th e powerspan ii pci master by reducing arbitration latency. 2.3.2 address phase the address phase deals with the generation of the pci address and command encoding. 2.3.2.1 command encoding the encoding on the px_c/be# li nes indicate the transaction type on the pci bus. the pci command encoding supported by powerspan ii, and their corresponding transaction types, are shown in table 7 .
2. pci interface 48 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com a new request for access to the bus is generated by the powerspan ii pci mast er when it requires access to the pci bus to service a request from th e processor bus interface or the other pci interface (py). after the request is generated by powerspan ii, it successfully arbitrates for access to the pci bus when it receives gnt_ from the arbiter. powers pan ii then asserts px_f rame# to indicate the beginning of a transaction. table 7: command encoding for transaction type (powerspan ii as pci master) px_c/be# [3:0] transaction type powerspan ii capable 0000 interrupt acknowledge yes (see ?configuration and iack cycle generation? on page 246 ) 0001 special cycle no 0010 i/o read yes 0011 i/o write yes 0100 reserved n/a 0101 reserved n/a 0110 memory read yes 0111 memory write yes 1000 reserved n/a 1001 reserved n/a 1010 configuration read yes (see ?configuration and iack cycle generation? on page 246 ) 1011 configuration write yes (see ?configuration and iack cycle generation? on page 246 ) 1100 memory read multiple yes 1101 dual address cycle no 1110 memory read line yes 1111 memory write and invalidate (the mwi_en bit is hard-wired to ?0? in the ?pci-1 control and status register.? on page 251 ) no
2. pci interface 49 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.3.2.2 address translation the address generated by the pci mast er is dependent on th e use of address tran slation in the source target image (see ?pci-1 target image x control register? on page 268 ) or slave image (see ?processor bus slave image x control register? on page 287 ). when address translation is enabled ? by setting the ta_en bit in pci target or pb slave image control register ? powerspan ii produces the pci address using the following inputs: ? the incoming address from the source bus ? the block size of the slave or target image ? the translation offset for address translation going from the processor bus to pci, see ?processor bus interface? on page 83 . for an example of address translati on control going from pci to pci, see ?pci-1 target image x translation address re gister? on page 274 . when address translation is disabl ed, the address generated by the pci master is the same as the address on the source bus.
2. pci interface 50 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.3.3 data phase the data phase deals with the control of burst length. 2.3.3.1 writes for non-dma writes, the length of the pci write transaction is dependent on the length of the transaction delivered from the source bus. writes originating from the processor bus can be either single cycle writes or burst writes. burst writes from the processor bus are always 32 bytes in length. this burst is converted to an 8 byte burst on a 32-bi t pci bus. either pci-1 or pci-2 can be configured as 32-bit. single cycle writes from the 64-bit processor bus are translated into two 8 byte burst writes on the 32-bit pci bus. this information is summarized in table 8 the pb master can also generate extended cycles. extended cycles are either 16 byte or 24 byte transactions. these cycles are en abled by setting the extended cycle (extcyc) bit to 1 in the ?processor bus miscellaneous control and status register? on page 304 . when the dual pci powerspan ii is used, incoming pci writes are executed as similar writes on the alternate pci interface. for exampl e, a 64-byte burst wr ite to memory space from the pci-1bus is executed as a 64-byte burst write to the memory sp ace on the pci-2 bus, provided the target on pci-2 does not disconnect. dma writes the powerspan ii dma channels always attempt to perfor m the longest possible burst ? up to 128-bytes ? on the pci bus. 2.3.3.2 reads the minimum memory read prefetch quantity is 8 bytes (default). setting the mem_io bit in the ?pci-1 target image x control register? on page 268 enables 1,2,3, or 4 byte memory reads on the pci bus. table 8: pb writes and their corresponding pci writes pb write 64-bit pci write 32-bit pci write 32-byte line write 4-beat 32-byte burst write 8-beat 32-byte burst write 8-byte single write single beat 8-byte write 2-beat 8-byte burst write write transactions intended for i/o space on the alternate pci bus must be single beat writes. bursting is not supported for a target image programmed to generate an i/o access on the alternate pci bus. a burst write directed at such a target image results in a target-disconnect after every data beat.
2. pci interface 51 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the powerspan ii pci master generates a memory re ad command selection according to the rules in table 9 . the read amount presented to th e pci master determines the comm and used. a memory read line command uses the burst lengt h programmed into the cline[7:0] field in the ?pci-1 miscellaneous 0 register? on page 255 . it is programmable to 16-, 32-, 64-, or 128 bytes. 2.3.3.3 parity monito ring and generation powerspan ii monitors px_par#/p x_par64# when it accepts data as a pci master during a read, and drives px_par#/px_par64# when it provides data as a pci master during a write. powerspan ii also drives px_par#/px_par64# during the address phase of a transaction when it is a pci master. in both address and data phases, the px_par#/px_par64# sign al provides even parity for px_c/be#[3:0] and px_ad[31:0]. even parity is enabled px_c/be#[7 :4] and px_ad[63:32] for pci-1 in 64-bit mode. powerspan ii parity response is enabled through the parity error response (peresp) bit in the ?pci-1 control and status register.? on page 251 . data parity errors are repo rted through the assertion of px_perr# when the peresp bit is set. the detected parity error (d_pe) bit in the ?pci-1 control and status register.? on page 251 is set when powerspan ii encounters a parity error as a pci master on any transaction. powerspan ii records an erro r condition in the event of a parity error (see ?error handling? on page 157 ). the master data parity de tected (mdp_d) bit in the ?pci-1 control and status register.? on page 251 is set if the peresp bit is enabled and either powers pan ii is the master of the transaction where it asserts perr#, or the addressed target asserts perr #. if the transfer origin ated from the processor interface, then powerspan ii sets the mdp_d bit and the px_pb_err_en bit in the ?interrupt enable register 1? on page 334 . powerspan ii then asse rts an interrupt (see ?interrupt handling? on page 145 ). table 9: powerspan ii pci master read commands internal request of transaction length pci memory read command <= 8 bytes memory read <= cline[7:0] in px_misc0 memory read line > cline[7:0] in px_misc0 memory read multiple if the pci master does not complete the burst read transaction before a target termination, it completes the read with subsequent pci read transactions at the appropriate address. powerspan ii continues with the transaction inde pendent of any parity errors reported during the transaction.
2. pci interface 52 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.3.4 terminations this section describes the termina tions supported by the powerspan ii, how they are mapped from the destination port to the pci ta rget, and exception handling. 2.3.4.1 pci master terminations the pci master supports all four types of pci terminations: 1. master-abort: the pci master negates px_f rame# and then negates px_irdy# on the following clock edge when no target responds wi th px_devsel# asserted on the fifth positive edge of clock after px_frame# is asserted. powe rspan ii sets r_ma in px_csr and records an error condition in the event of a master-abort (see ?error handling? on page 157 ) 2. target-disconnect (with data): a te rmination is requested by the target ? by asserting px_stop, px_devsel# and px_trdy# ? because it is unab le to respond within the latency requirements of the pci 2.2 specification or it requires a new address ph ase. target-disconnect means the transaction is terminated after da ta is transferred. powerspan ii negates px_req# for at least two clock cycles if it receives px _stop# from the pci target. 3. target-retry: termination is requested ? by asserting px_stop# and px_devsel# while px_trdy# is high ? by the target because it cannot currently process the transaction. retry means the transaction is terminat ed after the address phase without data transfer. powerspan ii has a maximum retry counter (max_retry) in the ?pci-1 miscellaneous control and status register? on page 283 which is used to record an error c ondition if the number of retries exceed the programmed amount (see ?error handling? on page 157 ). 4. target-abort: the target requests a termination of a transaction ? by negating px_devsel# and asserting px_stop# on the same clock edge ? when it cannot respond to the transaction, or during a fatal error. although there may be a fatal error for the initiating application, the transaction completes gracefully, ensuring no rmal pci operation for other pci resources. powerspan ii sets r_ta in px_csr and records an error condition in the event of a target-abort (see ?error handling? on page 157 ). 2.3.4.2 error logging and interrupts the powerspan ii pci master records e rrors under the following conditions: ? data parity on reads ( when the persp bit, in the ?pci-1 control and status register.? on page 251 , is set) ?master-abort ? target-abort ? expiration of maximum retry counter (when the max_retry field, in the ?pci-1 miscellaneous control and status register? on page 283 , is set. see ?error handling? on page 157 and ?interrupt handling? on page 145 for a full description of error logging support and associated interrupt mapping options.
2. pci interface 53 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.4 compactpci hot swap silicon support compactpci?s hot swap specification defines the process for installing and removing adapter boards without adversely affecting a runnin g system. it provides a programmat ic access to hot swap services. this enables system re-configurati on and fault recovery to take place with no system down time and minimum operator interaction. powerspan ii is compliant with the compactpci?s hot swap sp ecification, r evision 2.0 and is a hot swap silicon device. hot swap sili con support includes the following: ? open drain output pin enum# is used to indi cate hot swap insertion and extraction events. ? 5v tolerant input pin es for sensing the state of the ejector switch used to insert or extract a compactpci board. ? 5v tolerant open drain output pin led# for contro lling the blue light emitting (led) required to indicate status of the soft ware connection process. for the different levels of hot swap support, refer to the compactpci hot swap specification . to simplify the design of compac tpci hot swap adapter cards, powe rspan ii has addi tional support. this support includes: ? a 5v tolerant input pin healthy# for sensing the status of the back end power on the card. ? an input pin p1_64en# that enables hot swap adap ter cards to sense the presence of a 64-bit pci backplane. 2.4.1 led support the led can be controlled by hardware and softwa re. powerspan ii drives the led# signal low to turn on the led during the physical and hardware connection process (when healthy# is negated). a blue led with an internal resistor can be directly connected betw een the 5v rail and the led# signal. software controls the led by setting the led on/off (loo) bit in the ?pci-1 compact pci hot swap control and status register? on page 264 . 2.4.2 es input the compactpci hot swap specification defines a switch located in the ejector handle that indicates to powerspan ii if the ejector handle is open or closed. a low value on es input indicates that the ejector latch is open. a high value on es indicates that the ejector latch is closed and is in operation mode. 2.4.3 healthy# signal powerspan ii manages the electrical board level issu es involved in the hot swap process with the healthy# signal. the negation of healthy# indicates only some of the components on the hot swap card are powered. to operate in this environm ent and minimize long term reliability issues, the healthy# signal controls the electrical behavior of powerspan ii i/o buffers.
2. pci interface 54 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com during the negation of healthy#, powerspan ii disables its output and bidirectional pins ( except for led#) to avoid applying power to non-powered components on the card. the signals connected between powerspan ii and these non-powered componen ts result in floating pins on powerspan ii. powerspan ii uses healthy# to inhibit the input recei vers. an inhibited receiver has no static current path between supply and ground that could be activated by a voltage level near the switching point. see ?resets, clocks and power-up options? on page 167 for more details on healthy# and powerspan ii reset. 2.4.4 compactpci hot swap ca rd insertion and extraction a compactpci board has a staggered pin arrangeme nt (long/medium/short) to allow power and ground, signal and a board inserted indicator (bd_s el#) to be connected and disconnected in stages. a limited number of power and ground pins are long. the rest of the power, ground, and signal pins are of medium length. bd_sel# is a short pin. when bd_sel# connects, the phys ical connection process is complete. 2.4.4.1 compactpci hot swap process a compactpci hot swap board is divided into two power regions: early power and back end power. early power is provided by the long pins on the compactpci connector. back end power is controlled by a sequencer on the card. the sequencer begins to power the back end of the card when the short compactpci signal bd_sel# engages on insertion, or when host software enables the process as in a high availability system. in figure 7 , powerspan ii is designed into a compactpci adapter card. figure 7 assumes the compactpci b ackplane is not in reset during the insertion and extraction process. for example, powerspan ii?s p1_rst# is negated.
2. pci interface 55 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 7: powerspan ii in a compactpci adapter card ensure that pb_clk and p2_clk are within specification before the release of back-end power-up reset. long pins short pins long pins medium pins 5 v vio rp gnd rp vp precharge regulator 5 v 3.3v 2.5v p1_rst_dir "remaining pci-1 i/o" pb_rst_dir pb_clk "remaining pb i/o" p2_rst_dir p2_clk "remaining pci-2 i/o" gnd led# es long pins ejector/switch early power 5 v 3.3 v healthy# gnd hot swap supply sequencer 5 v 3.3 v power on reset oscillator regulator back end power 3.3 v 2.0 v clkin "remaining i/o" gnd host processor rst# clk "remaining i/o" gnd secondary pci 3.3 v bd_sel# healthy# p1_rst# enum# p1_64en# p2_rst# pb_rst_ 3.3 v po_rst_ compact pci pci-1/j1 connector gnd poreset_ hreset_ on_ powerspan ii
2. pci interface 56 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.4.5 hot swap insertion process use the application illustrated in figure 7 as a point of reference in the hot swap insertion process outlined below. 1. long pins contact for early power: ? healthy# negated ? powerspan ii resources are in reset ? led# pin enabled, st atus diode turned on ? powerspan ii output pins di sabled, input pins inhibited ? card?s pci signals pre-charge 2. medium pins contact pci backplane signals: ? powerspan ii?s primary pci interface, in this case pci-1, connects to the pci pins on the backplane ? powerspan ii p1_clk is within specification 3. short pins contact, bd_sel# asserted: ? back end power ramps ? back end power-up reset asserted ? powerspan ii po_rst_ asserted ? host processor poreset_ asserted, host processor asserts hreset_ ? clock generator be gins oscillation ? powerspan ii pb_clk and p2_clk begin to oscillate ? ejector switch closes some time after short pins contact 4. back end power is within specification: ? healthy# asserted ? led# pin disabled ? powerspan ii outputs enabled, pb_rst_ and p2_rst# asserted ? host processor and secondary pci clocks are with in specification 5. back end power-up reset negation: ? powerspan ii plls released from reset and begin to lock on to p1_clk, pb_clk, p2_clk
2. pci interface 57 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com ? host processor completes its configuration master transactions ? powerspan ii power-up options are loaded ? host processor hreset_ times out ? powerspan ii pll locking complete ? all powerspan ii resources out of reset, pb_rst_ and p2_rst# negated ? powerspan ii executes eeprom load or waits to be initialized by the processor 6. powerspan ii waits for the closed ejector switch and responds by: ? setting ins bit in the hs_csr register ? asserting enum# 7. powerspan ii is now able to accept configurat ion cycles on pci-1 fr om the compactpci host since px_lockout bit in the ?pci-1 miscellaneous control and status register? on page 283 ) defaults to 1, powerspan ii re tries the host configuration acc esses on the pci-1 interface until px_lockout is cleared. the host then negates enum# by clearing the insertion (ins) bit in the ?pci-1 compact pci hot swap contro l and status register? on page 264 and configures the card. the px_lockout bit is cleared by an eeprom load or by access from the processor interface. it is automatically cleared by powerspan ii when the pwru p_boot option is set to pci.
2. pci interface 58 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 8: hot swap insertion 2.4.6 hot swap extraction process use the application illustrated in figure 7 as a point of reference in th e hot swap extraction process outlined below. 1. ejector switch opens ? the extraction (ext) bit in the p1_hs_csr regi ster is set, causing the assertion of enum# 2. compact pci host: ? reads the p1_hs_csr of each agent to de termine which card is being extracted ? clears the powerspan ii ext bit. this causes the negation of enum# and arms the ins bit ? places the card in a so ftware dormant state ? sets the led on/off (loo) bit in the p1_hs_ csr register. this caus es the assertion of led# which turns the light emitti ng diode to signal the operator 3. operator begins extracting the card. at this point the operator can close the ejec tor switch and reenter the insertion process. ext bit ins bit led enum# ejector state pci signals pci clock pci rst# healthy# bd_sel# back end power early power med engage short engage fully seated clocking closed open engaged, tracking bus cleared/unarmed cleared/armed led off cleared/unarmed set cleared/unarmed physical connection hardware connection start of software connection process led on pre-charge pulled up long engage back-end powered board goes healthy (from j1) pre-charge pre-charge pre-charge clears loo bit ejector latched
2. pci interface 59 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 4. short pins break, bd_sel# is negated ? back end power goes out of specification ? healthy# negated ? all powerspan ii resources reset ? led# pin enabled, st atus diode turned on ? powerspan ii output pins disa bled, input pins inhibited ? pci pre-charge reapplied 5. medium pins break. 6. long pins break. figure 9: hot swap extraction after the status led# is illu minated by the host, the operator can close the ejector switch, rather than extracting the card. if the closure or the extraction occurs, a powerspan ii register reload from eeprom does not occur. ext bit ins bit led enum# ejector state pci signals pci clock pci rst# healthy# bd_sel# back end power early power ejector unlatched sw clear ext bit sw set loo bit withdrawal starts short disengage med. disengage long disengage clocking (from j1) closed open led off engaged, tracking bus cleared/unarmed cleared/armed led on cleared/armed set cleared/unarmed software connection hardware connection physical connection pre-charge pre-charge pre-charge pre-charge pulled up
2. pci interface 60 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.5 vital product data vital product data (vpd) is in formation which uniquely defines items of a system. these items include the hardware, software and microcode elem ents of a system. vpd also provides a mechanism for storing information, such as performance data on a device. vpd resides in a local storage device. powerspan ii supports vpd through the i 2 c interface to serial eepr om. the vital product data extended capabilities pointer an d supporting registers reside in the configuration space of the powerspan ii primary pci interface. the vpd feature requires the vpd_en bit, in the ?miscellaneous control and status register? on page 318 , to be set and an avai lable external eeprom. 2.5.1 vpd access vpd accesses through powerspan ii default to the i 2 c serial eeprom device zero (vpd eeprom chip select (vpd_cs) = 0b000 in the ?miscellaneous control and st atus register? on page 318 ). this is also used for eeprom loading of the registers after reset. sin ce the lower bytes in the eeprom contain data for setting up powers pan ii before software initialization, the lower portion of the eeprom ( the first 64 bytes) are not visible through the vpd regist ers. the upper 192 bytes of the 256 byte eeprom are visible through the vpd registers. of these bytes, the first 64 bytes are vpd-read only and the remaining 128 bytes are vpd-read/w rite. when vpd_cs = 0b000, vpd addresses are translated upward by 64 bytes before being presented to the eeprom. powerspan ii can be programmed with an alternate chip select for vpd access if more than the 192 accessible bytes is required. programming of the i 2 c chip select is done in the powerspan ii ?miscellaneous control and st atus register? on page 318 . if an alternate i 2 c chip select is used then the first 64 bytes of the vpd eeprom is designat ed as vpd-read only and the upper 192 bytes are designated as vpd-read/write. the vpd access to the eeprom is similar to the eeprom acces s implemented in powerspan ii through the i2c_csr register, except that it uses the ?pci-1 vital product data capability register? on page 266 and the ?pci-1 vital product data register? on page 267 . since they both access the same resource, a powerspan ii semaphore register semax mu st be used to acquire exclusive access of the i 2 c interface before softwa re initiates vpd accesses. 2.5.2 reading vpd data powerspan ii implements 8-bits of address for accessing the eeprom up to a maximum of 256 bytes. the vpd address must be dword-aligned. a single read access reads four consecutive bytes starting from the vpd address from the eeprom. if i 2 c chip select zero is used for vpd, then 192 bytes (address 0x00-bf) of vpd are accessible through the vpd read. using another i 2 c chip select, the vpd read can access the entire 256-byte eeprom address range.
2. pci interface 61 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com during a read access, the vpd address (vpda) fi eld and the vpd flag (f) bit are written in the ?pci-1 vital product da ta register? on page 267 . the f bit must be set to 0 to indicate a vpd read access. powerspan ii sets the f bit to 1 when it completes reading the 4 bytes from the eeprom. the f bit must be polled to determine when the read is complete. byte 0 (bits 7 through 0) of the ?pci-1 vital product data register? on page 267 contains the data referenced by the vpd address ? bytes 1 through 3 contain the successive bytes. 2.5.3 writing vpd data a write can only occur to the upper 128 bytes of the eeprom or, potentially , the upper 192 bytes if i 2 c chip select is non-zero. similar to the read op eration, the write operation always writes four consecutive bytes starting from the vpd address to the eeprom. the ?pci-1 vital product da ta register? on page 267 is written with the 4 bytes of data. byte 0 (register bits 7 - 0) contains the data to be writte n to the location referenced by the vpd address. bytes 1-3 contain the data for th e successive bytes. the vpda field and the f bit is then written. the f bit must be set to 1 to indicate a vpd write. the f bit is polled to determine when the write to the eeprom is completed. powerspan ii sets the f bit to 0 when the write is completed. when a write is attempted to the lower 64 bytes of the vpd area of the eeprom, powerspan ii does not perform the write operation and clears the f bit. if the px_vpdd register or the i2c_ csr register is written to prio r to the flag bit being set to 1, the results of the original read operation are unpredictable. the px_vpdd or i2c_csr register must not be written while a write op eration is occurring.
2. pci interface 62 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.6 i 2 o shell interface powerspan ii provides portions of the i 2 o shell interface for the platfo rm it is connecting to the primary pci bus. the i 2 o shell interface defined in the i 2 o 2.0 specification is comprised of three main sections: ? messaging interface ? protocol for exchanging messages ? executive class messages powerspan ii implements the i 2 o messaging interface and, in co njunction with the input/output processor (iop), enables the message passing protocol. 2.6.1 i 2 o target image there are three registers which enable memory access to the i 2 o shell interface and local iop message frames. the supporting registers include the following: ? ?pci-1 i2o target image base address register? on page 257 ? ?pci i2o target image control register? on page 352 ? ?pci i2o target image translat ion address register? on page 356 the i 2 o shell interface consists of inbound and outbound queues and supporting i 2 o host interrupt registers. the queues contain me ssage frame addresses (mfas). th ese mfas specify the starting address of message frames relative to the base address of the memory window in powerpc memory. powerspan ii implements i 2 o support with the first memory base address register in pci configuration space. the i 2 o target image is divided into an i 2 o shell interface and a proc essor bus memory window intended for iop message frame accesses. the i 2 o shell interface is accessed through the lower 4 kbytes of the i 2 o target image. i 2 o shell interface accesses are limited to 32-bit single data phase pci transactions. accesses through the i 2 o target image memory window to iop message frames are burstable up to 64-bits wide for pci-1, but limited to 32-bit wide for pci-2. powerspan ii does not suppo rt posting of more than one write transaction to the inbound or outbound queue. attempts to write to the inbound or outbound queue are retried until the currently active write completes on the processor bus interface. the i 2 o target image does not suppo rt master-based decode.
2. pci interface 63 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.6.2 iop functionality a number of configuration steps are required befo re powerspan ii and the embedded processor bus are enabled to provide iop functionality. the follow ing example assumes pci-1 is the primary pci interface. the steps required to implement io p functionality are listed below. 1. in order to identify powerspan ii as an i 2 o controller the ?pci-1 class register? on page 254 must be programmed as follows: ? base class code (base) = 0x0e ? sub class code (sub) = 0x00 ? programming interface (prog) = 0x01 2. the inbound and outbound queues? location and size in iop memory must be programmed in powerspan ii. this is accomplished by programming the ?i2o queue base address register? on page 360 : ? processor bus i 2 o base address (pb_i2o_bs): spec ifies base address of the queues ? fifo size (fifo_size): specifi es the size of the queues 3. the pci i 2 o target image must be configured to claim i 2 o shell and message frame accesses from pci. the following regist ers must be programmed: ? configure i 2 o image size with the bl ock size (bs) bit in ?pci i2o target image control register? on page 352 (pci_ti2o_ctl). ? enable base address register (bar) visibility in configuration space. ? set bar_en in the pci_ti2o_ctl register. ? program pci base address register ?pci-1 i2o target image base address register? on page 257 . ? set image enable (img_en) in ?pci i2o target image cont rol register? on page 352 to enable decode. note that this occurs if a non-zero value is written to the pci base address register. ? configure processor bus master transaction parameters. ? write transfer type (wtt) in the pci_ti2o_ctl register. ? read transfer type (rtt) in the pci_ti2o_ctl register. ? global command (gbl) in th e pci_ti2o_ctl register. ? cache inhibit (ci) in the pci_ti2o_ctl register. ? select endian conversion me chanism with the endian co nversion (end) bit in the pci_ti2o_ctl register programming values other than the ones li sted above do not affect the behavior of powerspan ii as an i2o device .
2. pci interface 64 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com ? configure address translation ? translation address en able (ta_en) bit in the pci_ti2o_ctl register. ? translation addr ess (taddr) in the ?pci i2o target image translation address register? on page 356 (pci_ti2o_taddr) ? enable decode in pci memory space. ? set memory space (ms) bit in the ?pci-1 control and status register.? on page 251 . at this stage, the i 2 o image is defined but all accesses to the pci i 2 o target image are retried. 4. the iop is required to initialize all top and bo ttom pointer registers and initialize all the mfas in the inbound free list fifo. at this point, the iop enables pci accesses wi th the foll owing step: ? set the i2o enable (i2o_en) bit in the ?i2o control and status register? on page 357 . 2.6.3 messaging interface the i 2 o 2.0 specification defines a mechanism for connecting an i/o platform (iop) to an i 2 o system through a memory-based system, su ch as pci, which has no inhere nt message passing capability. an iop which is connected to a memory -based system is said to be locally attached. the powerspan ii implements four i 2 o defined memory mapped registers on pc i to enable the physical and logical connection of the iop to the syst em. two of these memory-mapped re gisters provide the interface for the external host platform and other iops to exchange messages with the local iop sitting behind the powerspan ii. these two registers are the inbound queue and outbound queue interfaces. the other two registers are used as i 2 o specific interrupt status and enable registers for the local iop to signal the host platform. additional powerspan ii speci fic registers are implemented to support the messaging interface. 2.6.3.1 inbound queue the i 2 o inbound queue register is the messaging interface used by the host or external iop to post messages to the local iop. the i 2 0 inbound queue register interface is located at offset 0x040 of the powerspan ii pci i 2 0 target image in pci memory space. the in bound queue has a free list fifo and a post list fifo, both of which reside in the iop local memory. 2.6.3.2 inbound free list fifo and post list fifo the free list contains the mess age frame address (mfas) of mess age frames (mfs) in the iop?s local memory, which are availabl e to the host or other iops for writing inbound messages. the post list contains the mfas of mfs in the local iops memory which contain inbound messages for the iop to process.
2. pci interface 65 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the inbound mfas are 32-bit offsets from the translated powerspan ii i 2 0 target image window base address in local iop memory. when th e host platform or an external iop wishes to send a message to the local iop it must firs t obtain an mfa from the inbound free list . the external plat form is then free to place a message in the associated mf. the mfa is then placed into the inbound po st list for the local iop to process. 2.6.3.3 outbound queue the outbound queue register is th e messaging interface used by the local iop to post messages to the host. the i 2 o outbound queue register interface is locate d at offset 0x044 of the powerspan ii pci i 2 o target image in pci memory space. the outboun d queue has a free list fifo and a post list fifo, both of which reside in the iop local me mory. the free list contains the message frame address (mfas) of message frames (mfs) in the host system memory, whic h are available to the local iop for writing outbound messages. outbound mfas are absolute addresses of a message frame in host memory. the post list co ntains the mfas of mfs in the ho st system memory which contain outbound messages for the host to process. when the local iop wishes to send a message to the host platform it must first obt ain an mfa from the outbound free list. the local iop is then free to place a message in the associated mf. the mfa is then pla ced into the outbound post list for the host to process. all outbound messages are targeted for the host platform. if the local iop wishes to send a message to another iop (peer-to-peer communication) it uses the external iops inbound queue to post the message. 2.6.3.4 protocol for exchanging messages powerspan ii i 2 o registers the powerspan ii pci i 2 o shell interface implements the following i 2 o defined registers: ?i 2 o outbound post list in terrupt status register ?i 2 o outbound post list in terrupt mask register ?i 2 o inbound queue ?i 2 o outbound queue ?i 2 o host outbound index register (used for outbound option) in addition to the registers defined in the i 2 o 2.0 specification , powerspan ii implements a number of registers to support the i 2 o message passing protocol of the shell interface. ?pci i 2 o target image control register (pci_ti2o_ ctl) ?pci i 2 o target image translation addr ess register (pci_ti2o_ taddr) ?i 2 o queue base address re gister (i20_ queue_bs) all i 2 o inbound queue mfas must be offsets of greater than 4 kbytes.
2. pci interface 66 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com ? processor bus i 2 o base address field: base address of the block of iop memory that contains the four fifos (two inbound and tw o outbound). the base address alignment is 1 mbyte. ? fifo size field: indicat es the number of bytes required for each of the inbound queue and outbound queue fifos imple mented in local memory ?i 2 o control and status register (i20_ csr) ? host outbound post list size fiel d: indicates the number of entries in the host outbound post list fifo in host memory, used for the outbound option. ?i 2 o enable field: enables/ disables powerspan ii i 2 o interface ? powerspan ii primary pci target retries i 2 o accesses until enabled ?xi 2 o enable field : enables/disables powe rspan ii outbound option ? ipl: inbound post list is set when th e inbound post list fifo is not empty ? ofl: outbound free list is set when th e outbound free list fifo is not empty. ? inbound free list bottom/top/top increment pointer registers: (ifl_bot/ifl_top/ifl_top_inc) ? manages the inbound free list circul ar fifo implemented in local memory ? inbound post list bottom/bottom increment/top pointer registers: (ipl_bot/ipl_bot_inc/ipl_top) ? used to manage the inbound post list ci rcular fifo implemented in local memory ? outbound free list bottom/bottom increment/top pointer registers: (ofl_bot/ipl_bot_inc/ofl_top) ? used to manage the outbound free list ci rcular fifo implemen ted in local memory ? outbound post list bottom/top/t op increment poin ter registers: (ipl_bot/ipl_top_inc/ipl_top) ? used to manage the outbound post list ci rcular fifo implemented in local memory ? iop outbound index/increment registers: (iop_ oi/iop_oi_inc) ? used to manage the host outbound fifo ? host outbound index/index alias registers: (host_oi/host_oia) ? used to manage the host outbound fifo ? host outbound index offset registers: (host_oio) ? determines offset of the i 2 o target image at which the ho st processor can access the i 2 o host outbound index register interactions between the iop an d host platforms during the i 2 o message passing protocols are displayed in figure 3.4. the solid lines indicate po inters which are maintained and incremented by the powerspan ii. the dashed lines indicate pointers wh ich are incremented by the iop. the iop writes one to increment to powerspan ii incremen t register associated with the pointer.
2. pci interface 67 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 10: powerspan ii i 2 o message passing the top and bottom pointers manage external fifos to determine the full and/or empty status of the fifos. after a fifo write, the top pointer is increm ented. if the top pointer then equals the bottom pointer, a fifo full condition exists. after a fifo read, the bottom pointer is incremented. if the bottom pointer then equals the top po inter, a fifo empty condition exists. pci bus inbound queue (0x040) inbound free list fifo inbound post list fifo outbound free list fifo outbound post list fifo bottom pointer top pointer bottom pointer top pointer top pointer bottom pointer top pointer bottom pointer local processor (iop) inbound queue outbound queue outbound queue (0x044) local processor (iop)
2. pci interface 68 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.6.4 inbound messages the inbound free and post list fifos are impleme nted as circular queues using bottom and top pointers. the powerspan ii implements the bottom an d top pointers for the inbound free list fifo and the inbound post list fifo. the fifos reside in the local memory. the inbound posted messages also reside in local processor memory. when the host platform or external iop wants to post a message to the local iop, it must first acquire an mfa from the inbound free list . this is accomplished through a pci read transaction to the powerspan ii inbound queue register at offset 0x040 of the i 2 o target image. powerspan ii provides the next available mfa from the inbound free list fi fo pointed to by the inbound free list bottom pointer register. powerspan ii increments the inbound free list bottom pointer register to point to the next entry of the fifo. a read from the inbou nd queue register when the inbound free list fifo is empty (bottom pointer equal to top pointer) re turns 0xffff_ffff to the requesting pci master. once the host or external iop obtai ns an mfa, it is then to write a message to the iop?s local mf at the address offset from the px_bsi2o specified by th e mfa. once the message is transferred the host or external iop writes the mfa back to the same i 2 o target image offset (0x040). powerspan ii accepts the write transaction on pci and generate a writ e to the inbound post list fifo at the local iop memory address pointed to by the inbound post list top pointer register. powerspan ii then increments the inbound post list top pointer regist er and asserts the i2o_iop interrupt status bit in the isr0 register to notify the local processor of mfas in the inbound post list fifo. the ipl bit in the ?i2o control and status register? on page 357 is set while the inbound post list fifo is not empty, indicating that inbound message frames need to be processed. 2.6.4.1 local processor functions for inbound messaging, the local processor performs the following: ? detects the interrupt ? reads the powerspan ii isr0 register ? determines the source of the inte rrupt through the i2o_iop register ? clears the i2o_iop interrupt (write 1 to clear) ? reads the inbound post list fifo bottom pointer re gister to access the inbound post list fifo to get the mfa ? increments the inbound post list bottom pointer re gister by writing the inbound post list bottom pointer increment register ? reads and processes the mf pointed to by the mfa ? writes the mfa back to the top of the inbound free list fifo ? writes to the powerspan ii?s inbound free list to p pointer increment regi ster to increment the address by four ? reads the ipl bit, in the i2o_csr, to de termine if the inbound post list is empty the interrupt can be masked, leaving it to the pr ocessor to poll the isr register. a read from the inbound post list bottom pointer register by th e iop when the inbound po st list fifo is empty returns 0xffff_ffff to the processor if the emtr field of the i2o_csr re gister is set to one.
2. pci interface 69 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.6.5 outbound messages the outbound free and post list fifos are implem ented as circular queues using bottom and top pointers. powerspan ii implements the bottom and top pointers for the outbound free list fifo and the outbound post list fifo. when the local iop wants to post a message to th e host, it must first acquire an mfa from the outbound free list. the iop read s the mfa pointed to by the outbound free list bottom pointer register. the processor then increm ents the outbound free list bottom pointer register by four to point to the next entry of the fifo. the iop, having obtained a host mfa, is then free to write a message through the powerspan ii to the host mf at the host memory addr ess specified by the mfa. once th e message is transferred, the iop writes the mfa to the outbound post list fifo at the address pointed to by the outbound post list top pointer maintained by powerspan ii. the proces sor then increments the outbound post list top pointer register by four. while the outbound post list fifo is non-empty powerspan ii sets an interrupt status bit in the powerspan ii i 2 o outbound post list interrupt status register of the i 2 o target image (0x030). if the interrupt is not masked by the powerspan ii outbound post list interrupt mask register of the i 2 o target image (0x034), powerspan ii drives an interru pt to notify the host processor of mfas in the outbound post list fifo. powers pan ii determines the outbound po st list fifo to be non-empty when the outbound post list fifo bottom and top pointers do not point to the same fifo address. 2.6.5.1 host processor functions for outbound messaging, the host processor performs the following: ? detects the interrupt. ? reads the i 2 o outbound post list interrupt status register (0x030). ? reads the outbound queue re gister at offset 0x044 of the powerspan ii i 2 o target image map to obtain the next out bound post list mfa. ? processes the message pointed to by the mfa. the outbound interrupt status and mask bits are aliased in i2o_host in the ?interrupt status register 0? on page 327 and i2o_host_mask in the ?interrupt status re gister 0? on page 327 . the iop must program i2o_host_map in the ?interrupt map register miscellaneous? on page 346 in order for the outbound interrupt to be routed to powerspan ii?s primary pci interrupt pin. 2.6.5.2 outbound message fr ame addresses (mfa) powerspan ii provides the mfa at the bottom of the outbound post list fifo by performing a delayed read from the processor bus. the powerspa n ii increments the outbound post list bottom pointer register and compares the value with the outbound post list top pointer to determine if the outbound post list fifo is empt y. when the bottom and top pointers contain the same value the i 2 o outbound post queue interrupt status bit is cleared by the powerspan ii. alternatively, the interrupt can be masked out, leaving it to the host proces sor to poll the outbound queue register. when the outbound post list fifo is empty, the powerspan ii returns 0xffff_ffff when the host processor reads the outbound queue register.
2. pci interface 70 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com once the host processor has processed the mfa, it writes the mfa back to the outbound queue register (0x044) to place it back in the outbou nd free list fifo. powerspan ii accepts the write transaction and takes resp onsibility for replacing the mfa in the outbound free list fifo at the address pointed to by the outbound free list top po inter register. powerspan ii then increments the outbound free list top pointer register by four. 2.6.6 pull capability the i 2 o 2.0 specification defines an enhancement th at allows the iop to prov ide a capability to pull the i 2 o inbound messages from the host memory. in this configuration the host places the i 2 o inbound messages in mfs located in the host memory as opposed to the iop local memory. the host must also implement a host free list fifo in ho st memory. this fifo does not replace the iop inbound free list fifo, which must still be implemented in the iop local memory to support normal inbound message passing, or peer to-peer message passing. this capability increases server performance by virtue of the host cpu and server platforms being optimized for memory access rather than i/o access. under this option , the host can post inbound messages to the iop with a single write to the iop. the iop pulls the mf from the host memory and releases a mf to the host by generating a single write to host memory. the pull capability applies only to the iop?s inbound queue and to the posting of messages by the host. the pull model requires 16 byte alignment of the mess age frames, therefore, th e least significant four bits of the mfa are always zero. the pull options use these four bits to create an extended mfa (xmfa). the pull model uses the least significant bit of the xmfa to indicate a pull request. this bit is the pull indicator or the p bit. bits 3:1 of the xmfa indicate the number of data transfers required to copy the message. this nu mber is system specific and has no ef fect on the powerspan ii?s behavior. to prevent overflow of the local inbound post li st fifo the iop reports an inbound post list headroom to the host, which is th e difference between the size of th e inbound post list fifo and the total number of iop inbound message frames allo cated by the iop in local memory. this is the number of xmfas the host can post to the i 2 o inbound post list fifo and guarantee not to overflow the inbound post list fifo. the iop must not alloca te more mfas in the inbound free list than can be accepted in the inbound post list (a long with xmfas) wit hout causing overflow. equation ? #inbound free mfas + #xmfas <= fifo_size (see ?i2o queue base address register? on page 360 for more information) 2.6.6.1 host posting the host can post a message to th e iop using the pull capability by using the following methods: ? reading an xmfa from the host free list fifo ? writing an inbound message to the mf in host memory indicated by the xmfa ? writing an xmfa to the inbound queu e register at offset 0x040 of the i 2 o target image on pci the xmfa is processed by the powerspan ii in the sa me way as a normal mfa posted to the local iop by the host or external iop. the iop can determine if the xmfa is posted using the pull capability and to pull the message from the system memory. to release an xmfa back to the host platform the iop writes the xmfa back to the host free list fifo which resides in system memory.
2. pci interface 71 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.6.6.2 host free list address the address and size of the host free list fifo is provided to the iop by the i 2 o system host in an i 2 o defined ?iop message pull extens ions? message. the host free list fifo structure is located at a memory boundary equal to its size to enable the iop to know wh en it has reached the end of the fifo. when the iop returns xmfas to the host free list fifo sets the p bi t to 1. when the iop reaches the end of the fifo resets the fifo index to the base address and this time through write the p bit to 0. this allows the host to track the progress of the local iop in returning xmfas. figure 11 illustrates the following steps in powerspan ii i 2 0 pull capability: 1. host reads xmfa from host free list 2. host writes message to mf in host memory 3. host writes xmfa to inbound queue 4. local processor reads xmfa fro m the inbound post list fifo 5. local processor copies mf from host memory 6. local processor wr ites xmfa to host free list index
2. pci interface 72 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 11: powerspan ii i 2 o pull capability pci bus inbound queue (0x040) inbound free list fifo inbound post list fifo host free list fifo bottom pointer top pointer bottom pointer top pointer top pointer bottom pointer local processor (iop) inbound queue host platform host free list index host processor mfa headroom (xmfa) xmfa step 1 xmfa step 3 step 6 step 4 step 6 xmfa step 5 step 3
2. pci interface 73 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.6.7 outbound option the i 2 o 2.0 specification allows for the iop to provide an enhan ced capability to po st reply messages to the host. this mechanism is independent of the pull capability of the previous section. this capability reduces the number of reads that the host mu st perform to the iop. under the outbound option operation, the local iop c opies out the reply message to th e host system memory and then posts the message by performing a single write to th e host memory. the host need only to write to the powerspan ii to re turn the mfa. the outbound option requires 16-byte alignment of the message frames and th us the least significant four bits of the mfa are always zero. the outbound option uses these four bits to create and extended mfa (xmfa). the least significant bit of the outbound xmfa is the cycle indicator bit or the c bit. 2.6.7.1 host posting to post a message to the host, the iop completes the following: 1. obtains an outbound mfa from the outbound free list fifo. 2. copies out the reply message to the mf i ndicated by the host allocated outbound mfa. 3. posts the outbound mfa to the hostpostlist fifo pointed to by the iop outbound index register, setting the least significant bit of the mfa to 1, and increment the iop outbound index register by writing to the iop ou tbound index increment register. the powerspan ii iop outbound inde x register is initialized by the iop with a value received along with the host outbound post list fifo size through an ?iop message outbound extensions? message from the host. the size of the host outbound post list fifo is specified in the hopl_size bit in the i2o_csr register. the powerspan ii iop outbound index register points to the top of the host outbound post list fifo implemented in host memory. when it reach es the end of the fifo the iop resets the iop outbound index register to the base of the fifo. the iop writes xmfas to the fifo with the c bit set to 0, and continues to alternate this pattern. this allows the host to determine where the iop processor has last written to the fifo. powerspan ii also implements a ho st outbound index register where the host will write its host outbound post list fifo index after servicing outbound reply messages po sted using the outbound option. the host outbound index register points to the bottom of the host outbound post list fifo. powerspan ii maps this register into the powerspan ii i 2 o target image shell in terface at the offset specified in the i 2 o host outbound index offset register. this register is initia lized by the iop with an offset provided by the host through th e iop message outbound extensions message. when i 2 o extended capabilities are enabled with i2o_csr[xi2o_en], powe rspan ii will set an interrupt status bit in the i 2 o outbound post list interrupt status register when the i 2 o host outbound index register is not equal to the i 2 o iop outbound index register. th is indicates that the host outbound post list fifo is non-empty.
2. pci interface 74 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com powerspan ii compares the value of the host ou tbound index register to the iop outbound index register. if they are identical the interrupt is cleare d by the powerspan ii. if th ese registers differ, then it is assumed that the powerspan ii has posted addi tional outbound reply messages which have not yet been serviced by the host, and therefore, the powerspa n ii continues to assert th e interrupt to the host. the host will post empty mfas back to the iop by writi ng to the powerspan ii?s outbound queue register (0x044), with the c bit set to zero. powerspan ii services the written mfa the same as a normal outbound mfa being returned to the iop. figure 12 illustrates the following steps in powerspan ii i 2 0 outbound capability: 1. local processor reads the outboun d free list to obtain an mfa 2. local processor writes th e mf in the host memory 3. local processor writes the mfa to the host outbound po st list fifo, setting the p bit 4. host processor reads the xmfas from the host outbound post list 5. host writes the xmfa to the outbound queue (0x044)
2. pci interface 75 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 12: powerspan ii i 2 o outbound capability pci bus host outbound post list fifo outbound free list fifo iop outbound index host outbound index top pointer bottom pointer host processor host platform outbound queue outbound queue (0x044) local processor (iop) xmfa step 1 xmfa step 3 step 5 step 4 step 5 xmfa step 3 xmfa xmfa
2. pci interface 76 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.6.8 i 2 o standard registers this section defines the standard i 2 o register set supported by powerspan ii. these registers are accessible within the powerspan ii i 2 o target image. in table 10 , all standards-based registers are in italics. the i 2 o shell interface is located in the first 4 kbytes of the powerspan ii i 2 o target image. the i 2 o inbound message frames occupies offsets a bove the 4 kbyte point of the powerspan ii i 2 o target image. the upper limit of the i 2 o inbound message frames is determined by the size of the powerspan ii i 2 o target image, as defined by the pci_i2o_ctl[bs] register. the offset of the i 2 o host outbound index register is programmed in the i 2 o host outbound index offset register (host_oio) of the powerspan ii register map. the following tables show the i 2 o register definitions. table 10: powerspan ii i20 target image map offset (hex) register mnemonic register name 0x000-028 powerspan ii reserved 0x030 opl_is i 2 0 outbound post list interrupt status register 0x034 opl_im i 2 0 outbound post list interrupt mask register 0x038 powerspan ii reserved 0x040 in_q i 2 0 inbound queue 0x044 out_q i 2 0 outbound queue 0x048-[host_oio]-4 powerspan ii reserved [host_oio] host_oi i 2 o host outbound index register [host_oio]+4-0xff powerspan ii reserved 0x100-xxx i 2 0 inbound message frames
2. pci interface 77 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.6.9 i 2 0 outbound post list inte rrupt status register the i 2 0 2.0 specification requires the outbound post_list interrup t status register to be located at offset 0x30 in the memory region specified by the firs t base address register (i 2 0 base address register - px_bsi2o). when the i 2 0 messaging unit in powerspan ii is enable d (i2o_csr[i2o_en] = 1), a memory access from pci to offset 0x30 from px_b si2o is destined for opl_is. when the i 2 0 messaging unit in powerspan ii is not enabled, the opl_is register is not visible to read or write access. the register essentially disa ppears from all powerspan ii memory maps. register name: opl_is register offset: 030 pci bits function ppc bits 31-24 i 2 o reserved 0-7 23-16 i 2 o reserved 8-15 15-08 i 2 o reserved 16-23 07-00 i 2 o reserved opl_ isr i 2 o reserved 24-31 name type reset by reset state function opl_isr r px_rst 0 outbound post list interrupt service request 0 = outbound post_list fifo is empty 1 = outbound post_list fifo is not empty. the value of the interrupt mask bit does not affect this bit.
2. pci interface 78 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.6.10 i 2 0 outbound post list in terrupt mask register. the i 2 0 2.0 specification requires the outbound post_list interrup t mask register to be located at offset 0x34 in the memory region specifie d by the first base address register (i 2 0 base address register - px_bsi2o). when the i 2 0 messaging unit in powerspan ii is enable d (i2o_csr[i2o_en] = 1), a memory access from pci to offset 034h from px_b si2o is destined for opl_im. when the i 2 0 messaging unit in powerspan ii is not enabled, the opl_im register is not visible to read or write access. the register essentially disa ppears from all powerspan ii memory maps. register name: opl_im register offset: 034 pci bits function ppc bits 31-24 i 2 o reserved 0-7 23-16 i 2 o reserved 8-15 15-08 i 2 o reserved 16-23 07-00 i2o reserved op_ism i 2 o reserved 24-31 name type reset by reset state function op_ism r/w px_rst 0 outbound post_list interrupt mask 0 = outbound post_list interrupt is enabled 1 = outbound post_list interrupt is masked
2. pci interface 79 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.6.11 i 2 0 inbound queue a read from the i 2 o inbound queue returns the ne xt available mfa from the i 2 o inbound free list fifo. this is a destructive read. a write to this offset is us ed to place a mfa into the i 2 o inbound post list fifo. the powerspan ii accepts the write cycle as a posted write and is res ponsible for completing the cycle on the destination bus. when the i 2 0 interface in powerspan ii is not enabled, the in _q register is not visible to read or write access. the register essent ially disappears from all po werspan ii memory maps. register name: in_q register offset: 040 pci bits function ppc bits 31-24 mfa 0-7 23-16 mfa 8-15 15-08 mfa 16-23 07-00 mfa 24-31 name type reset by reset state function mfa[31:0] r/w px_rst 0 inbound message frame address the inbound message frame address specifies locations in the iop memory map where inbound message frames reside. the mfa is the offset from the beginning of the i 2 o target image window in the destination bus memory map and the destination address where the message frame begins.
2. pci interface 80 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.6.12 i 2 0 outbound queue a read from the i 2 o outbound queue returns the next mfa from the i 2 o outbound post list fifo. this is a destructive read. a write to this offset place s a free host mfa into the i 2 o outbound free list fifo. powerspan ii accepts the write cycle as a posted write and is res ponsible for completing the cycle on the destination bus. when the i 2 0 interface in powerspan ii is not enabled, the out_q register is not visible to read or write access. the register es sentially disappears from al l powerspan ii memory maps. register name: out_q register offset: 044 pci bits function ppc bits 31-24 mfa 0-7 23-16 mfa 8-15 15-08 mfa 16-23 07-00 mfa 24-31 name type reset by reset state function mfa[31:0] r/w px_rst 0 outbound message frame address the outbound message frame address specify locations in the host memory map where outbound message frames reside. the message frame address is the host memory address of the message frame.
2. pci interface 81 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 2.6.13 i2o host outbound index register this register indicates the address in host memory from which the host is to retrieve the next outbound xmfa. this register is initialized by the iop wi th an index received from the host in an i 2 o message. the register is written by the host during i 2 o outbound option message passing. when the i 2 o host outbound index register and the i 2 o iop outbound index register differ, the outbound post list interrupt status bit is set in the opl_is register at offset 0x30 of the pci i 2 o target image. when these registers cont ain the same host memory addr ess, the interrupt is cleared. this feature is only supported if the i 2 o outbound option is enabled with the xi2o_en bit in the i2o_csr register and i2o_en. the hopl_size bit in the i2o_csr register dete rmines the alignment of this index register. the register offset is specified in the i 2 o host outbound index offset re gister at offset 0x548 of the powerspan ii register map. the i 2 o host outbound index register must be located in the lower 4 kbytes of the pci i 2 o target image map. when the i 2 0 interface in powerspan ii is not enabled, the host_oi register is no t visible to read or write access. the register es sentially disappears from al l powerspan ii memory maps. register name: host_oi register offset: [host_oio] pci bits function pb bits 31-24 oi 0-7 23-16 oi 8-15 15-08 oi 16-23 07-00 oi 0 0 24-31 name type reset by reset state function oi[29:0] r/w px_rst 0 host outbound index
2. pci interface 82 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com
83 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 3. processor bus interface this chapter describes the functionality of the proc essor bus interface. both the single pci powerspan ii and dual pci powerspan ii have a processor bu s interface. the following topics are discussed: ? ?overview? on page 83 ? ?pb slave interface? on page 84 ? ?pb master interface? on page 100 3.1 overview the powerspan ii processor bus (pb) interface directly connects with a wide range of processors in order to meet the demands of high end systems, the pb interface operates up to100 mhz and has a 64-bit data bus. 3.2 interface support the powerspan ii processor bus interface su pports the following em bedded processors: ? motorola: powerquicc ii (mpc825x, mp c826x, mpc827x, mpc8280), powerpc 7xx (mpc74x, mpc75x), powerpc 7400 ? ibm: powerpc 740, powerpc 750 ? wintegra: winpath tm although these interfaces are not iden tical, for the most part the proc essor interface on the powerspan ii is referred to simply as the pro cessor bus (pb). the interface sections in this chapter highlight where the powerspan ii operates differently to address speci fic processor requirements as the need arises. an example of this different operation is th e extended cycles wi th the powerquicc ii. 3.2.1 terminology the following terms are used in the processor bus interface descriptions: ? address retry window : refers to the clock following the assertion of aack_, which is the latest a snooping master can request for an address tenure re-run. ? window of opportunity: refers to the clock following the assertion of artry_. the retrying master has to request the bus on this clock to ensure that it is the ne xt bus owner. this enables it to perform the transactions require d to maintain cache coherency. the powerquicc ii and powerpc 7400 must operate in 60x compatible bus mode to be used with powerspan ii. in single powerquicc ii m ode the processor cannot share the bus with other external masters.
3. processor bus interface 84 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 3.2.2 pb bus interface descriptions the pb bus interface is described in terms of it s master and slave functions. the pci interfaces on powerspan ii are described in terms of its pci mast er and pci target functio ns. this description is largely independent of pci-1 versus pci-2, or the assignment of the primary pci interface functions. exceptions to these rules are noted in the manual. 3.2.2.1 transaction ordering for information on powerspan ii?s pci transaction or dering refer to ?transaction ordering? on page 34 . 3.3 pb slave interface powerspan ii becomes active as a pb slave when one of the following conditions occurs: ? a processor bus master accesses a pci resource, generating a memory or i/o space access ? a processor bus master accesses a pci resour ce, generating a configuration or iack access ? a processor bus master accesses powerspan ii registers this section covers the first two of these conditions. see ?register access? on page 235 for a discussion of the last two items in the bullet list above. the operation of the pb slave is described below by dividing the pb slav e transaction into the following different phases: ? address phase: this section discusses the decoding of processor bus accesses. ? data transfer: this section descri bes control of transaction length. ? terminations: this section describes the terminat ions supported by powerspan ii, and exception handling. pull-up resistors are not required on the proces sor bus address (pb_a[0:31 ]) and data (pb_d[0:63]) signals to guarantee functional oper ation of powerspan ii. however, adding resistors to the address and data signals minimizes the current drawn by the powerspan ii's tristated buffers when the bus is in an idle condition. the system designer must decide whet her to add these resistors to the address and data bus. the powerspan ii pb slave supports cacheable ac cesses to pci, but it does not guarantee coherency if more than one pr ocessor accesses a given range of memory. in order to address this issue, operating system pages mapped to powerspan ii must have the memory coherency attribute (m) set to zero. powerspan ii performs pci read prefetches. these reads can be cached in an internal queueing memory within powerspan ii ? if prkeep is set to 1. when a write is performed to a prefetched ad dress, a subsequent read yields stale data. prefetching attributes for each image map must meet the systems cache coherency requirements.
3. processor bus interface 85 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 3.3.1 address phase the address phase deals with the de coding of processor bus accesses. 3.3.1.1 transaction decoding transaction decoding on the pb slav e operates in both normal decode mode and master-based decode mode. when powerspan ii is in normal decode mode, eac h pb slave monitors the processor bus address (pb_a[]). when the address falls into one of the programmed windows, and the transfer type (pb_tt[]) is supported, powerspa n ii claims the address tenure. pb slave image location is controlled by se tting the base address (ba) field in the ?processor bus register image base address register? on page 295 . pb slave image size is controlled by setting the block size (bs) field in the ?processor bus slave image x control register? on page 287 . powerspan ii supports eight general purpose slave im ages and four specialty slave images. a general purpose slave image generates memory or i/o reads and writes to the pci bus. for example, the eight general purpose slave images can support the loca l bus traffic of four powerquicc ii sccs, two threads of cpu traffic destined for pci-1, and two threads destined for pci-2. the speci alty images are used for the generation of pci configuration cycles on pci-1 and pci-2, iack reads on pci-1, iack reads on pci-2 and powerspan ii register accesses. the pb slave image also co ntrols how an incoming pb transaction is mapped to the destination port on powerspan ii. for example, there are bits fo r endian mapping, pref etch behavior, etc. table 11 on page 86 describes the programming model for a pb slave image control register. the pb slave image only claims a transaction when all of th e following conditions are met: ? the external address matches the slave image ? the transaction codes are supported a pb slave image is defined as the range of processor bus physical address space that decodes a powerspan ii access. in normal decoding mode (see ?transaction decoding? on page 85 ), the pb slave image claims transactions initiated by the powerspan ii pb master interface if the transaction meets the two conditions listed above. in order to avoid the pb slave from claiming transactions from the a transaction powerspan ii pb mast er interface, the master-based decode functionality can be enabled.
3. processor bus interface 86 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com table 11 describes the bits and default settings of the ?processor bus slave image x control register? on page 287 . table 11: programming model for pb slave image control register bits type description default setting img_en r/w enables the pb slave image to decode in the specified physical address range. disabled ta_en r/w enables address translation (see ?processor bus slave image x translation address register? on page 292 ). disabled bs[4:0] r/w sets the block size of the pb slave image. the size of the image is 4 kbyte * 2 bs . default value is 0. it can be programmed through any port after reset, or loaded through eeprom. mode r/w maps the incoming pb transaction to either memory or i/o space on the pci bus. defaults to memory space. dest r/w directs the incoming pb transaction to either of pci-1 or pci-2 defaults to pci-1 mem_io r/w enables 1,2,3, or 4 byte memory reads on the pci bus(es). regular i/o mode prkeep r/w enables powerspan ii to keep prefetch read data over subsequent transactions. disabled end[1:0] r/w sets endian mapping to little-endian, powerpc little-endian, or big-endian big-endian is the default mode. rd_amt[2:0] r/w controls the prefetch read amount. can be programmed up to a maximum of 128 bytes. 8 bytes is the default prefetch read amount pb memory management supports a variet y of memory/cache acce ss attributes: write through (w), caching-inhibite d (i), and memory coherency (m ). although powerspan ii does not decode these attributes ? extern al pins pb_gbl_ and pb_ci_ are output only? specific guidelines must be followed to ensure corr ect system operation. these guidelines are shown in table 12 . table 12: recommended memory/cache attribute settings powerspan ii resource memory coherency caching inhibited registers m=0 i=1 pci i/o space m=0 i=1 pci memory space m=0 external l2 cache: i=1 no external l2 cache: i=0 or 1
3. processor bus interface 87 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com master-based decode mode the pb slave interface supports master-based decode mode when the internal powerspan ii processor bus arbiter is enabled (see ?processor bus arbitration? on page 141 ) and the master decode enable (md_en) bit is set in the ?processor bus slave image x co ntrol register? on page 287 . when master-based decode is enabled, a pb slave image only claims a transaction decoded for its specified physical address space if it originates fro m specific processor bu s master or masters. external bus masters are selected for a specific target by setting one or more of the m1 to m3 bits in the ?processor bus slave image x transl ation address register? on page 292 . the pb slave image only claims a transaction when all of th e following conditions are met: ? the address matches the slave image ? the transaction codes are supported ? mx is set and the identified ma ster is requesting a transaction 3.3.1.2 transfer types the pb slave only claims processo r bus transactions with specific transfer types. the supported transfer types consist of address only, read, and write. they are defined in table 13 . all reads are treated as delayed reads and can be single cycle, extended or burs ts. all writes are treated as posted writes and can be single cycle, extended or bursts. powerspan ii handles address only cycles by asserting pb_aack_ ? no data transfer occurs. address only transfer types are claimed to ensure powerspan ii does not negatively impact cache control, reservation, or ordering transactions on the processor bus. register and pci i/o space accesses requires i to be set to 1 because powerspan ii does not accept burst transactions to these resources. powerspan ii behavior is undefined if mo re than one identically programmed, or overlapping, slave image claims a transaction. for example, if two slave image have the same base address and size, then they must have unique master bits set in the ?processor bus slave image x translation address register? on page 292 . table 13: powerspan ii pb slave transfer types tt[0:4] name address only 00000 clean block 00100 flush block 01000 sync block 01100 kill block
3. processor bus interface 88 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com because powerspan ii does not have a cache, all read and write transfer types are treated the same. for example, a read with intent to modify command (p b_tt= 01110) is handled the same way as a read atomic command (pb_tt= 11010). powerspan ii performs pci read prefetches and stores read data in an internal buffer when the prefetch keep (prkeep) bit is set to 1. the purpose of a pref etch read is to fetch read information before the master requests the information. if the master then requests the in formation the target can respond immediately with the prefetched information. this abil ity protects the master from slow access times for information it requires. however, when a write is performed to a prefetched address, a subsequent read could yield stale data. in orde r to guarantee there is no stale data , set the prkeep bit to 0. this function disables the internal buff er to ensure there is no stale data. by setting this prkeep bit to 0 powerspan ii is unable to perform pci read prefetches and read perfo rmance may be decreased in the system. 10000 eieio 11000 tlb invalidate 00001 lwarx 01001 tlb sync 01101 icbi reads 01010 read 01110 read with intent to modify 11010 read atomic 11110 read with intent to modify atomic 01011 read with no intent to cache writes 00010 write with flush 00110 write with kill 10010 write with flush atomic prefetching attributes for each image map must meet the system?s cache coherency requirements table 13: powerspan ii pb slave transfer types tt[0:4] name
3. processor bus interface 89 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 3.3.1.3 address tenure each slave on the pb interface is responsible for the following: ? decoding the address broadcast by the master ? claiming the address tenure with pb_aack_ assertion ? managing the data termination signals during the data tenure the pb slave uses pb_aack_ to limi t the level of address pipelining to one. the earliest the pb slave can assert pb_aack_ is two clocks after pb_ts_. the pb slave does not acknowledge subsequent address phases until it finishes its participation in the current data tenure. if the previous address phase was claimed by another slave, the pb slave does not acknowledge the current address phase until th e previous slave completes its data tenure. the use of pb_artry_ by the pb slave is enabled by the address retry enable (artry_en) bit in the ?processor bus miscellaneous control and status register? on page 304 . if the artry_en bit is set to 0, the pb_artry_ signal is not asserted and the pb slave retains owners hip of the bus. the pb slave retains ownership after the assertion of pb_ aack_ and until it is able to assert pb_ta. when artry_en has a value of 1, the pb slave can assert pb_artry_. th e default setting is 0 (artry_en is disabled). the pb in terface has higher performance if the artry_en bit is enabled. powerspan ii?s pb master or another external mast er can gain access to the bus when powerspan ii cannot assert pb_ta. when artry_en is enabled, th e pb slave asserts pb_artry_ in the following situations: ? a write destined for pci ca nnot be internally buffered ? when a read request has been latched an d read data is be ing fetched from pci ? a register access when a lo ad from eeprom is in progress ? writing to registers when another bus (pci-1, pci-2) is also writing to the register block if the assertion of pb_artry_ is enabled, it occurs the clock after pb_aack_ within the address retry window . 3.3.1.4 address translation the incoming address on the pb interface can ha ve a translation offset applied to it using the taddr[19:0] field of the ?processor bus slave image x transl ation address register? on page 292 . when the translation offset is appl ied to the incoming pb address, th e translated address appears on the destination bus (pci-1 or pci-2). th e translation offset replaces the pb address, up to the size of the image. taddr[19:0] replaces pb address lines pb_a[0:19].
3. processor bus interface 90 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com for example, if taddr[19:0] = 0x12345 and the bs bit in the pb_six_ctl register equals 0 (4-kbyte image) and the address on the processo r bus is pb_a[0:31] = 0x78563412, then the pci address becomes 0x12345412. table 14 summarizes the relationship between translation offset, processor bus address, and block size of the image. table 14: translation address mapping pb_six_taddr processor bus address (pb_a) bs bit (pb_six_ctl register) block size 31 0 10011 2g 31:30 0:1 10010 1g 31:29 0:2 10001 512m 31:28 0:3 10000 256m 31:27 0:4 01111 128m 31:26 0:5 01110 64m 31:25 0:6 01101 32m 31:24 0:7 01100 16m 31:23 0:8 01011 8m 31:22 0:9 01010 4m 31:21 0:10 01001 2m 31:20 0:11 01000 1m 31:19 0:12 00111 512k 31:18 0:13 00110 256k 31:17 0:14 00101 128k 31:16 0:15 00100 64k 31:15 0:16 00011 32k 31:14 0:17 00010 16k 31:13 0:18 00001 8k 31:12 0:19 00000 4k
3. processor bus interface 91 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 3.3.1.5 address parity address parity checking is provided on each byte of the address bus. address parity bit assignments are defined in table 15 . when the pb slave detects an address parity error du ring its decode process it does not assert address acknowledge (pb_aack_). address parity checking is enabled with the address parity enable (ap_en) bit in the ?processor bus miscellaneous contro l and status register? on page 304 . odd parity versus even parity is configured with the parity bit in the same register. special parity requirement s with the powerquicc ii address parity and data parity must be specially programmed in a joint powerspan ii and powerquicc ii application. in a joint application all memory accesses from the powerquicc ii to powerspan ii must be routed through the internal memory controller on the po werquicc ii. when the data is passed through the memory controller both address parity and data parity can be used in the system. if accesses do not pass through the memory cont roller of the powerquicc ii before reaching powerspan ii, and powerspan ii has either or both ad dress and data parity en abled, then powerspan ii reports parity errors on the transaction. to enable or disable address parity in powerspan ii, set the address parity enable (ap_en) bit in the ?processor bus miscellaneous control and status register? on page 304 . to enable or disable data parity in powerspan ii , set the data parity enable (ap_en) bit in the ?processor bus miscellaneous control and status register? on page 304 table 15: powerspan ii pb address parity assignments address bus address parity pb_a[0:7] pb_ap[0] pb_a[8:15] pb_ap[1] pb_a[16:23] pb_ap[2] pb_a[24:31] pb_ap[3]
3. processor bus interface 92 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 3.3.2 data phase the data phase deals with the control of transaction length. 3.3.2.1 transaction length the pb slave supports a set of the data transfer sizes supported by the embedded powerpc family. all data transfer sizes supported by the po werspan ii pb slave are illustrated in table 16 . burst transfers are indicated by the assertion of processor bus transfer burst (pb_tbst_). the shaded regions indicate transaction sizes un ique to the powerquicc ii. 3.3.2.2 data alignment embedded processor bus transfer sizes and alignments, defined in table 16 and table 17 , are supported by the pb slave for transaction acc esses. the shaded table cells in table 17 show transactions that support the powerpc 7400 processor. table 17 lists the size and alignment transactions less than or equal to 8 bytes. powerspan ii register accesses are limited to 4 bytes or less. table 16: powerspan ii pb transfer sizes transfer size bytes pb_tbst pb_tsiz[0] pb_tsiz[1:3] byte 1 1 0 001 half-word 2 1 0 010 tri-byte 3 1 0 011 word 4 1 0 100 five bytes 5 1 0 101 six bytes 6 1 0 110 seven bytes 7 1 0 111 double word (dw) 8 1 0 000 extended double (powerquicc ii only) 16 1 1 001 extended triple (powerquicc ii only) 24 1 1 010 burst (quad dw) 32 0 0 010 the powerspan ii port size is 64-bit.
3. processor bus interface 93 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com table 17: powerspan ii processor bus single beat data transfers size tsiz[0:3] a[29:31] data bus byte lanes 01234567 byte 0001 000 d0 0001 001 d1 0001 010 d2 0001 011 d3 0001 100 d4 0001 101 d5 0001 110 d6 0001 111 d7 half word 0010 000 d0 d1 0010 001 d1 d2 0010 010 d2 d3 0010 011 d3 d4 0010 100 d4 d5 0010 101 d5 d6 0010 110 d6 d7 tri-byte 0011 000 d0 d1 d2 0011 001 d1 d2 d3 0011 010 d2 d3 d4 0011 011 d3 d4 d5 0011 100 d4 d5 d6 0011 101 d5 d6 d7
3. processor bus interface 94 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com powerpc 7400 transaction support the powerpc 7400 processors supports misali gned transactions within a d ouble word (64-bit aligned) boundary. as long as the transaction does not cross the double word boundary, the powerpc 7400 can transfer data on the misaligned address. powerspan ii supports a specific types of the powerpc 7400 misaligned transactions (shown in table 17 ) when the mode_7400 bit is set in the ?processor bus miscellane ous control and status register? on page 304 . any misaligned transaction between powerspan ii and the powerpc 7400 that is a single word (32-bit) or less must be within a single word al igned boundary. any transfer greater than a single word must start or end on a word boundary. word 0100 000 d0 d1 d2 d3 0100 001 d1 d2 d3 d4 0100 010 d2 d3 d4 d5 0100 011 d3 d4 d5 d6 0100 100 d4 d5 d6 d7 five bytes 0101 000 d0 d1 d2 d3 d4 0101 001 d1 d2 d3 d4 d5 0101 010 d2 d3 d4 d5 d6 0101 011 d3 d4 d5 d6 d7 six bytes 0110 000 d0 d1 d2 d3 d4 d5 0110 001 d1 d2 d3 d4 d5 d6 0110 010 d2d3d4d5d6d7 seven bytes 0111 000 d0d1d2d3d4d5d6 0111 001 d1d2d3d4d5d6d7 double word 0000 000 d0 d1 d2 d3 d4 d5 d6 d7 the information in table 17 is independent of endian consider ations and pertains to byte lane control on the processor bus. for e ndian considerations, please consult ?endian mapping? on page 177 . software must make sure that the powerpc 7400 does not initiate unsupported misaligned transactions to powerspan ii . table 17: powerspan ii processor bus single beat data transfers size tsiz[0:3] a[29:31] data bus byte lanes
3. processor bus interface 95 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 3.3.2.3 cache line size the supported embedded powerpc processors impleme nt a 32-byte cache line si ze. cache wrap reads are supported by the pb slave for burst and extended transactions. 3.3.2.4 reads address retry enable the pb slave supports up to eight concurrent delayed reads when the address retry enable (artry_en) bit in the ?processor bus miscellaneous contro l and status register? on page 304 is set to 1. refer to ?concurrent reads? on page 27 for more information on re ad pipelining in powerspan ii. when an external master makes an initial read request, the powerspan ii pb slave latches the address. this initiates a read on the destination bus. the destination bus is specified by the destination bus (dest) bit in the ?processor bus slave image x c ontrol register? on page 287 . delayed reads the outstanding read is referred to as a delayed re ad. delayed reads consist of the following phases: 1. delayed read request ? powerspan ii pb slave latches trans action parameters a nd issues a retry 2. delayed read completion ? the pb slave obtains the requested data a nd completion status on the destination bus 3. read completion ? the master repeats the transaction with the same parameters used for the initial request any attempt by a processor bus master to complete the read transaction is retried by the powerspan ii pb slave until the following byte quantities are available in the line buffer: ? 32 bytes ? 8 bytes if the rd_amt=0 (see ?processor bus slave image x control register? on page 287 ) ? 16 bytes if the rd_amt=1 read amount all powerspan ii pb slave reads destined for pci me mory space are considered prefetchable to 8-byte boundaries by default. setti ng the mem_io bit in the ?processor bus slave imag e x control register? on page 287 enables 1,2,3, or 4 byte reads from the pci bus(es). powerpc processors do not generate cache wrap writes.
3. processor bus interface 96 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com in order to program powerspan ii to complete 4 byte reads on the pb bus, both the mem_io bit and the mode bit must be set to 1 in the processor bus slave image x control register. in order to perform a 4-byte read from the processo r (60x) bus to pci, the following bits must be programmed: ? mem_io bit set to 1 ? mode bit set to 1 ? end bit, in the ?processor bus slave image x control register? on page 287 , must not be set to little-endian mode (00). it can be set to po werpc little-endian (01) , or big-endian (10). the amount of data prefetched on the destination bus is specified using the prefetch read amount (rd_amt[2:0]) field in the ?processor bus slave image x control register? on page 287 . if the prefetch keep (prkeep) bit is set, then powerspa n ii automatically increm ents the latched address every time the processor bus master returns for read data. this prke ep function enables a burst read by the powerspan ii pci master to be unpacked as smaller transfers on the processor bus. the pb interface can generate a 32- byte burst read with a starting addr ess at the second, third or fourth 8-byte quantity. a cache wrap read always causes th e pb slave to make a 32-b yte read request from the destination pci bus. in other words, prkeep and rd_amt[2:0] have no effect. there are instances where a read requires more data than that specified by rd_amt. since pb slaves cannot terminate transactions, powerspan ii compensates for a potential hang situation ? for example, not having enough read data ? by over-riding the programming of rd_amt. powerspan ii prefetches the larger data value. this enables the powerspan ii to accommodate the byte count specified by the transaction. alternatively, it initiates a new read transaction on the destination if it does not have enough data to satisfy the transaction. the read amount values that can be prog rammed in the rd_amt field are shown in table 18 . the read amount setting determines different va lues to prefetch fro m the destination bus. when the slave image control register is programmed for 4 byte read transactions, requesting 8 byte reads causes undefined results in the system. table 18: read amount settings rd_amt[2:0] data fetched 000 8 bytes 001 16 bytes 010 32 bytes 011 64 bytes 100 128 bytes 101-111 reserved
3. processor bus interface 97 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com discard timer each pb slave image has a discard timer. if an external master does no t claim data within 2 15 clocks after data is read from the destination bus, the de layed read request latch is de-allocated. this prevents deadlock conditions. read buffer contents are flushed but there is no error recorded and no interrupts are generated. posted writes posted writes have dedicated line buffers and are treated independently of reads. a write to an image does not invalidate the contents of the read line buffer currently in use. address retry disabled the pb slave supports a single read at a time wh en artry_en is disabled. artry_en is disabled by setting the bit to 0. the pb slave acknowledges the address tenure with the pb_aac k_ signal and captures the address in the delayed read latch. ho wever, when artry_en is disabled, the pb slave does not acknowledge the data transfer unti l the read amount (rd_amt) field in the ?processor bus slave image x control register? on page 287 is read. the delayed read request latch is de-allocated when the external processor bus master completes the transaction. prkeep has no affect when pkeep is set to 1 and artry_en is disabled. a maximum of 32 bytes can be programmed in the rd_amt field. 3.3.2.5 writes all writes are posted and are buffered separately fro m read data. the transaction length of the pb write is directly translated to the pci bus with no address phase dele tion. for example, a single cycle write on the pb results in a single cycle write on the pci bus. 3.3.2.6 data parity data parity is enabled by setting the data parity enable (dp_en) bit in the ?processor bus miscellaneous control and st atus register? on page 304 . even parity or odd parity is enabled by setting the parity (parity) bit in the same register. parity generation and checking is provided for each byte of the data bus and for each data beat of the data tenure. data parity bit assi gnments are as defined in table 19. table 19: powerspan ii pb data parity assignments data bus data parity pb_d[0:7] pb_dp[0] pb_d[8:15] pb_dp[1] pb_d[16:23] pb_dp[2] pb_d[24:31] pb_dp[3] pb_d[32:39] pb_dp[4]
3. processor bus interface 98 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the data parity bits, pb_dp[0:7], are driven to the co rrect values for even or odd parity by the pb slave during reads and check ed during writes. the detection of a data parity error does not affect the transaction and data is still forwarded to the destination bus. see ?error handling? on page 157 and ?interrupt handling? on page 145 for a full description of error logging support a nd associated interrupt mapping options. special parity requirement s with the powerquicc ii address parity and data parity must be specially programmed in a joint powerspan ii and powerquicc ii application. in a joint application all memory accesses from the po werquicc ii to powerspan ii must be routed through the internal me mory controller on the powerquicc ii. when the data is passed through the memory controller both ad dress parity and data parity can be used in the system. if accesses do not pass through the memory cont roller of the powerquicc ii before reaching powerspan ii, and powerspan ii has either or both ad dress and data parity enab led, then powerspan ii reports parity errors on the transaction. to enable or disable address parity in powerspan ii, set the address parity enable (ap_en) bit in the ?processor bus slave image x control register? on page 287 . to enable or disable data parity in powerspan ii , set the data parity enable (dp_en) bit in the ?processor bus slave image x control register? on page 287 . 3.3.3 terminations the following sections describe the terminations and exception ha ndling supported by powerspan ii. 3.3.3.1 pb slave termination the pb slave uses the following pins to indicate termination of indivi dual data beats and/or data tenure: ? address retry (pb_artry_): this signal terminates the entire address and data tenure and schedules the transaction to be reru n. no data is transferred, even if asserted coin cidentally with pb_ta/pb_dval_, as in the case of a third party address retry. ? transfer acknowledge (pb_ta_): this signal is as serted by the powerspan ii pb slave to indicate the successful transfer of a single beat transactio n, or each 8-byte quantity transferred for a burst. pb_d[40:47] pb_dp[5] pb_d[48:55] pb_dp[6] pb_d[56:63] pb_dp[7] table 19: powerspan ii pb data parity assignments data bus data parity
3. processor bus interface 99 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com ? data valid (pb_dval_): this signal is asserted by the pb slave to indicate the successful transfer of an 8-byte quantity within an extended transfer of 16 or 24 bytes. pb_ta_ is asserted together with pb_dval_ on the transfer of the last 8-byte quantity. ? transfer error acknowledge (pb_ tea_): this signal indicates an unrecoverable error and causes the external master to immedi ately terminate the data tenure. 3.3.3.2 assertion of pb_tea_ powerspan ii asserts pb_tea_ when a particular sl ave image cannot handle transactions involving more than 4 bytes. this applies to the following: ? register accesses (see ?register access? on page 235 ) ? accesses to general purpose slave image configured for pci i/o space ? access to registers designed to generate pci configuration or iack commands (see ?configuration and iack cy cle generation? on page 246 ) powerspan ii also asserts pb_tea _ if a read from pci generates a master-abort or target-abort. the assertion pb_tea_ is enabled or disabled with the tea enable (tea_en) bit in the ?processor bus miscellaneous control and status register? on page 304 . 3.3.3.3 errors the powerspan ii pb slave detects the following error conditions: ? address parity ? data parity on writes ? illegal accesses see ?error handling? on page 157 and ?interrupt handling? on page 145 for a full description of error logging support and associated interrupt mapping options. the pb slave does not assert a data termination signal earlier than the address retry window . in a development environment, the tea_en bit is set to allow the assertion of pb_tea_ to support the debug of software. in a production en vironment, customers may find it useful to disable the assertion of pb_tea_.
3. processor bus interface 100 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 3.4 pb master interface the powerspan ii becomes active as pb master when: ? powerspan ii is accessed as a pci target ? one of the powerspan ii dma en gines is processing a transfer the operation of the pb master is described by di viding a transaction into three different phases: ? address phase: this section discus ses the arbitration for the addres s bus, and generation of the pb address and transfer types. ? data transfer: this section describes arbitration for the data bus, and cont rol of transaction size and length. ? terminations: this section describe s the terminations supported by powerspan ii, and exception handling. 3.4.1 address phase the address phase deals with the ar bitration for the address bus, and generation of the pb address and transfer types. 3.4.1.1 address bus arbitration and tenure the pb master asserts address bus busy (pb_abb_ ) to indicate address bus ownership after it receives a qualified bus grant for its address bus re quest. a qualified bus grant assumes the following: ? address bus grant asserted ? pb_artry_ negated ? address bus not busy the pb master negates pb_abb_ fo r at least one clock after address acknowledge (pb_aack_) has been asserted by the slave. this is true even if the arbiter parked the bus on powerspan ii. for example, in figure 13 on page 105 the bus is parked at the powerspan ii (pb_bg[1]_ is asse rted throughout), pb_abb_ is negated the first positive clock edge after sampling pb_aack_. the pb master operates in a multi-processor, ca che-coherent powerpc envi ronment that requires correct implementation of the window of opportunity . the following pb master behavior supports the window of opportunity : ? respond to pb_artry_ in the address retry window ? snoop pb_artry_ the powerspan ii pb master derives equiva lent address bus busy information from processor bus control si gnals. this allows the powerspan ii processor bus arbiter to operate in 60x environments that do not implement abb. the powerquicc ii uses abb to qualify address bus grants generated by the system arbiter.
3. processor bus interface 101 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com negating address bus requests when the pb master (as current address bus owne r) detects address retry (pb_artry_) asserted during the address retry window, it negates its bus request for at leas t one clock. this guarantees the snooping master that retried the cycle an opportuni ty to request and be granted the bus before the powerspan ii pb master can restart its transaction. on ce the bus is re-acquired, the pb master restarts the transaction. cache coherency the global (pb_gbl_) and cache in hibit (pb_ci_) parameters are programmable for each pci target image and dma channel (gbl and ci in the ?pci-1 target image x control register? on page 268 and the ?dma x attributes register? on page 317 ). assertion of pb_gbl _ during a pb master transaction instructs all processors on the bus to snoo p the transaction. control of this parameter allows the user to implement non-coherent accesses in specific areas of memory . assertion of pb_ci_ prohibits external agents from cachi ng the transaction. this ability is useful in a system with an l2 look aside cache. the pb master, along with all othe r bus masters, are required to snoop artry_ when they are not the bus owner. if artry_ is asserted, the masters must ensure the following actions are taken: ? release bus request, if it is asserted, for at least one clock ? do not acquire the bus if presently granted ? do not assert bus request during the window of opportunity to ensure a transaction is retried, systems assert pb_artry_ at, or before, the first assertion of pb_ta_. this timing avoids a data tenure being terminated after data is transferred between bus agents. normally, a retry scenario implies pb_art ry_ assertion one clock after assertion of the pb_aack_ ? in the address retry window. in certai n systems however, the fi rst assertion of pb_ta can occur before pb_aack_. if this situation occurs, pb_artry_ must be asserted at the same time as the first assertion of pb_ta_ and must be held until the cl ock after pb_aack_ assertion. address pipelining the pb master can operate in a system that implemen ts up to one level of address pipelining. the pb master does not prohibit other bus ag ents from pipelining transactions. internal and external arbitration when the powerspan ii processor bus arbiter is enabled (see ?arbitration? on page 137 ) all processor bus master address bus requests and grants are intern al to powerspan ii. when an external arbiter is used, the pb master requests the address bus on pb_br[1]_ and receives grants on pb_bg[1]_. for example, powerspan ii?s intern al arbiter is disabled in figure 13 on page 105 . when mastering the bus, the pb master can be gin a new address tenure before the current data tenure completes.
3. processor bus interface 102 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 3.4.1.2 address translation the address generated by the pb ma ster is dependent on the use of address translation in the source target image (see ?pci-1 target image x control register? on page 268 . when address translation is enabled ? ta_en bit is set in the pci target image ? powerspan ii produces the processor bus address using three inputs: ? the incoming address from the source bus ? the block size of the target image ? the translation offset this does not apply to dma transfers because the destination addres s is assumed to have the necessary offset by design. for more information, see ?dma x destination address register? on page 310 . 3.4.1.3 transaction type the transfer type parameter of a pb master transact ion, pb_tt, is specified with the pci target image or dma channel registers. the fo llowing registers control the pa rameter for write transactions: ? wtt[4:0] field in the ?pci-1 target image x control register? on page 268 ? wtt[4:0] field in the ?dma x attributes register? on page 317 the following registers control the parameter for read transactions: ? rtt[4:0] field in the ?pci-1 target image x control register? on page 268 ? rtt[4:0] field in the ?dma x attributes register? on page 317 the default transfer type generated by the po werspan ii pb interface master is shown in table 20 . 3.4.1.4 address parity address parity generation is provid ed on each byte of the address bu s. address parity bit assignments are defined in table 21 table 20: default powerspan ii pb master transfer type pb master transaction pb_tt[0:4] processor bus command writes 00010 write with flush reads 01010 read table 21: powerspan ii pb address parity assignments address bus address parity pb_a[0:7] pb_ap[0] pb_a[8:15] pb_ap[1]
3. processor bus interface 103 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com during pb master transactions, pb_ap[0:3] is driven to the correct values for ei ther even parity or odd parity. odd versus even parity is controlled with the parity bit in the ?processor bus miscellaneous control and status register? on page 304 . 3.4.2 data phase the data phase deals with arbitrat ion for the data bus, and control of transaction size and length. 3.4.2.1 data bus arbitration and tenure the pb master generates a data bus request by driving transfer type (pb_tt[3]) high during assertion of transfer start (pb_ts_). the pb master assert s data bus busy (pb_dbb_) to indicate data bus ownership when it receives a qualified bus grant (see figure 13 on page 105 ). a qualified bus grant includes: ? data bus grant (dbg) signal asserted ? pb_artry_ negated ? data bus not busy the pb master negates pb_dbb_ for at least one cl ock after the final data termination signal is asserted by the slave. pb_a[16:23] pb_ap[2] pb_a[24:31] pb_ap[3] if the dbg signal is asse rted past the data tenure of a tr ansaction, the pb master sees the assertion of the dbg signal as a new data tenure and re-asserts pb_dbb_. external slaves must not indicat e a successful data transfer with the assertion of pb_ta_ and/or pb_dval_ earlier than two clocks after the assertion of pb_ts_. to ensure powerquicc ii compliance with this rule, the powerquicc ii register bcr[apd] must be programed to a value greater than one. this parameter specifies the earliest time after assertion of pb_ts_ that the powerquicc ii slave asserts pb_ta_ to complete a data transfer. the bcr[apd] parameter is suppor ted by the powerquicc ii to accommodate processor bus agents with a range of sno op response times. bcr[apd] must be programmed to accommodate the slowest sno oping device in the system. the powerspan ii pb master deri ves equivalent data bus busy informatio n from pb control signals. this allows the powerspan ii proces sor bus arbiter to operate in processor bus environments that do not implement dbb. so me processors (for example the powerquicc ii) use dbb to qualify data bus gran ts generated by the system arbiter. table 21: powerspan ii pb address parity assignments address bus address parity
3. processor bus interface 104 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 3.4.2.2 transaction length the pb master can generate a super-set of the data transfer sizes supported by the embedded powerpc family. the user can disable certain data transfer si zes that are unique to the powerquicc ii. all data transfer sizes supported by the powers pan ii pb master are illustrated in table 22 below. burst transfers are indicated by the assertion of processor bus transfer burst (pb_tbst_, see figure 13 and figure 14 ). pb_tbst_ is negated during single cycle transactions (see figure 15 and figure 16 below). the shaded regions in table 22 indicate transaction si zes that are unique to the powerquicc ii. the extended cycles supported by the po werquicc ii are identified with an additional size pin, processor bus transfer size (pb_tsiz[0]). extended cycl es are enabled using the extcyc bit in the ?processor bus miscellaneous control and status register? on page 304 . the following figures, figure 13 and figure 14 , illustrate burst reads and burst writes on the pb master. powerspan ii only interfa ces to 64-bit slaves. table 22: powerspan ii pb transfer sizes transfer size bytes pb_tbst pb_tsiz[0] pb_tsiz[1:3] byte 1 1 0 001 half-word 2 1 0 010 tri-byte 3 1 0 011 word 4 1 0 100 five bytes 5 1 0 101 six bytes 6 1 0 110 seven bytes 7 1 0 111 double word (dw) 8 1 0 000 extended double (powerquicc ii only) 16 1 1 001 extended triple (powerquicc ii only) 24 1 1 010 burst (quad dw) 32 0 0 010
3. processor bus interface 105 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 13: pb master interface burst read figure 14: pb master interface burst write the following figures, figure 15 and figure 16 , illustrate single cycle r ead and single cycle write transfers on the pb master interface. pb_clk pb_a[0:31] pb_ap[0:3] pb_tsiz[0:3] pb_tt[0:4] pb_d[0:63] pb_dp[0:7] pb_tea_ pb_ta_ pb_dval_ pb_dbb pb_dbg_in_ pb_artry_ pb_aack_ pb_tbst_ pb_ts_ pb_abb_ pb_bg[1]_ pb_br[1]_ 0a pb_clk pb_a[0:31] pb_ap[0:3] pb_tsiz[0:3] pb_tt[0:4] pb_d[0:63] pb_dp[0:7] pb_tea_ pb_ta_ pb_dval_ pb_dbb pb_dbg_in_ pb_artry_ pb_aack pb_tbst_ pb_ts_ pb_abb_ pb_bg[1]_ pb_br[1]_ 02
3. processor bus interface 106 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 15: pb master interface single cycle read figure 16: pb master interface single cycle write 3.4.2.3 data alignment embedded processor bus transfer size s and alignments are supported by the powerspan ii pb master for transaction accesses. the pb master creates the necessary sequence of transactions from a set of processor bus data size and alignment options . the size and alignment combinations defined in table 24 are supported by the powerquicc ii, powerpc 7xx, and powerpc 750 processors. this set includes: ? transactions less than or equal to 8-bytes (s ingle beat transactions) ? specific misalign ed transactions ? extended transactions of 16 or 24-bytes ? burst of 32-bytes pb_clk pb_a[0:31] pb_ap[0:3] pb_tsiz[0:3] pb_tt[0:4] pb_d[0:63] pb_dp[0:7] pb_tea_ pb_ta_ pb_dval_ pb_dbb_ pb_dbg_in_ pb_artry_ pb_aack_ pb_tbst_ pb_ts_ pb_abb_ pb_bg[1]_ pb_br[1]_ 0a pb_clk pb_a[0:31] pb_ap[0:3] pb_tsiz[0:3] pb_tt[0:4] pb_d[0:63] pb_dp[0:7] pb_dval_ pb_tea_ pb_ta_ pb_dbb_ pb_dbg_in_ pb_artry_ pb_aack_ pb_tbst_ pb_ts_ pb_abb_ pb_bg[1]_ pb_br[1]_ 02
3. processor bus interface 107 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com table 23 illustrates the lanes used to carry each byte of a multi-byte structure on a 64-bit processor data bus. table 23: 64-bit pb data bus byte lane definitions byte address pb byte lanes pb_a[29:31] lane number powerspan ii pins powerquicc ii pins powerpc 7xx pins winpath pins 000 0 pb_d[0:7] d[0:7] dh[0:7] h_data[63:56] 001 1 pb_d[8:15] d[8:15] dh[8:15] h_data[55:48] 010 2 pb_d[16:23] d[16:23] dh[16:23] h_data[47:40] 011 3 pb_d[24:31] d[24:31] dh[24:31] h_data[39:32] 100 4 pb_d[32:39] d[32:39] dl[0:7] h_data[31:24] 101 5 pb_d[40:47] d[40:47] dl[8:15] h_data[23:16] 110 6 pb_d[48:55] d[48:55] dl[16:23] h_data[15:8] 111 7 pb_d[56:63] d[56:63] dl[24:31] h_data[7:0]
3. processor bus interface 108 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com table 24 lists the size and alignment transactions less than or equal to 8-bytes . the shaded table cells show transactions that support the powerpc 7400 processor. table 24: powerspan ii processor bus single beat data transfers size tsiz[0:3] a[29:31] data bus byte lanes 01234567 byte 0001 000 d0 0001 001 d1 0001 010 d2 0001 011 d3 0001 100 d4 0001 101 d5 0001 110 d6 0001 111 d7 half word 0010 000 d0 d1 0010 001 d1 d2 0010 010 d2 d3 0010 011 d3 d4 0010 100 d4 d5 0010 101 d5 d6 0010 110 d6 d7 tri-byte 0011 000 d0 d1 d2 0011 001 d1 d2 d3 0011 010 d2 d3 d4 0011 011 d3 d4 d5 0011 100 d4 d5 d6 0011 101 d5 d6 d7
3. processor bus interface 109 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com powerpc 7400 transaction support the powerpc 7400 processors supports misali gned transactions within a d ouble word (64-bit aligned) boundary. as long as the transaction does not cross the double word boundary, the powerpc 7400 can transfer data on the misaligned address. powerspan ii supports a specific types of the powerpc 7400 misaligned transactions (shown in table 24 ) when the mode_7400 bit is set in the ?processor bus miscellaneous control and status register? on page 304 . any misaligned transaction between powerspan ii and the powerpc 7400 that is a single word (32-bit) or less must be within a single word al igned boundary. any transfer greater than a single word must start or end on a word boundary. word 0100 000 d0 d1 d2 d3 0100 001 d1 d2 d3 d4 0100 010 d2 d3 d4 d5 0100 011 d3 d4 d5 d6 0100 100 d4 d5 d6 d7 five bytes 0101 000 d0 d1 d2 d3 d4 0101 001 d1 d2 d3 d4 d5 0101 010 d2 d3 d4 d5 d6 0101 011 d3d4d5d6d7 six bytes 0110 000 d0 d1 d2 d3 d4 d5 0110 001 d1 d2 d3 d4 d5 d6 0110 010 d2 d3 d4 d5 d6 d7 seven bytes 0111 000 d0 d1 d2 d3 d4 d5 d6 0111 001 d1 d2 d3 d4 d5 d6 d7 double word 0000 000 d0 d1 d2 d3 d4 d5 d6 d7 the information in table 24 is independent of endian consider ations and pertains to byte lane control on the processor bus. for e ndian considerations, please consult ?endian mapping? on page 177 . software must make sure that the powerpc 7400 does not initiate unsupported misaligned transactions to powerspan ii. table 24: powerspan ii processor bus single beat data transfers size tsiz[0:3] a[29:31] data bus byte lanes
3. processor bus interface 110 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 3.4.2.4 cache line size the powerpc processors supported by powerspan ii implement a 32-byte cache line size (8 words). cache wrap bursts are not generated because the pb master starts a burst transaction at a 32-byte aligned address. for a transaction th at is not 32-byte aligned, the pb master utilizes one or more single beat or extended transaction size, to align to the cache line bounda ry, before generating the required burst transaction or transactions. 3.4.2.5 data parity data parity is enabled by setting the dp_en bit in the processor bus control an d status register (see ?processor bus miscellaneous control and status register? on page 304 ). even or odd parity can be enabled by setting the parity bit on the pr ocessor bus control and status register. parity generation and checking is provided for each byte of the data bus and for each data beat of the data tenure. data parity bit assignments are as defined in table 25 . the data parity bits, pb_dp[0:7], ar e driven to the correct values fo r even or odd parity by the pb master during writes. if checking is enabled (by setting the dp_e n bit) the data parity bits, pb_dp[0:7], are checked by the pb master during read s. the detection of a data parity error does not affect the transaction, and data is still forwarded to the destination. see ?error handling? on page 157 and ?interrupt handling? on page 145 for a full description of error logging support and associated interrupt mapping options. the powerspan ii pb master assumes all exte rnal slaves can accept burst transactions. table 25: powerspan ii pb data parity assignments data bus data parity pb_d[0:7] pb_dp[0] pb_d[8:15] pb_dp[1] pb_d[16:23] pb_dp[2] pb_d[24:31] pb_dp[3] pb_d[32:39] pb_dp[4] pb_d[40:47] pb_dp[5] pb_d[48:55] pb_dp[6] pb_d[56:63] pb_dp[7]
3. processor bus interface 111 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 3.4.3 terminations the pb master uses the following pi ns as termination signals for indivi dual data beats and data tenure: ? address retry (pb_artry_): this signal terminates the entire data tenure and schedules the transaction to be rerun. no data is transferred. ? transfer acknowledge (pb_ta_): this signal is as serted by the external slave to indicate the successful transfer of a single beat transaction, or each 8 byte quantit y transferred for a burst. ? data valid (pb_dval_): this sign al is asserted by the external slave to indicate the successful transfer of a quantity of data. the powerquicc ii provides this pin to support the termination of extended cycles. the external slav e asserts this pin once for each successful 8 byte transfer. pb_ta_ is asserted, with pb_dval_, on the fina l transfer of the transaction. the slave uses pb_ta_ and/or pb_dval_ to insert wait stat es. the pb master ignores pb_dval_ when the extcyc bit cleared in the ?processor bus miscellaneous co ntrol and status register? on page 304 . ? transfer error acknowledge (pb_ tea): this signal indicates an unrecoverable error and causes the pb master to immediately terminate the data tenure. 3.4.3.1 errors the pb master detects three error conditions: ? data parity on reads ? assertion of pb_tea_ by external slave ? expiration of maximum retry counter (max_retry bit in the ?processor bus miscellaneous control and status register? on page 304 ). see ?error handling? on page 157 and ?interrupt handling? on page 145 for a full description of error logging support and associated interrupt mapping options.
3. processor bus interface 112 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com
113 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 4. dma a direct memory access (dma) channel allows a tr ansaction to o ccur between two devices without involving the host processor (for example, a read transaction between a peripheral device and host processor memory). because less time is required to complete transactions, applications that contain one or more dma channels support fa ster read and write transfers than applications that support only host-assisted transactions. discusses the following topics about the powerspan ii dma: ? ?dma register description? on page 114 ? ?direct mode dma operation? on page 118 ? ?linked-list mode dma operation? on page 120 ? ?dma interrupts? on page 124 ? ?dma error handling? on page 124 4.1 overview powerspan ii has four iden tical direct memory access (dma) cha nnels for independent data transfer between the three ports of the dual pci powerspan ii: processo r bus interface (pb) , pci interface 1 (pci-1) and pci interface 2 (pci-2). the programmin g and operation of the four dmas are the same. this chapter discusses dm a operation within the context of a sing le channel. in addition, since the dmas are able to transfer data from any port to any port, the dma discussion refers to ?source? bus and ?destination? bus with no reference to bus type. exceptions to this guideline are noted in the manual. there are two modes of operation for the powerspan ii dma: direct mode a nd linked-list mode. in direct mode, the dma control registers are directly programmed for each dma transfer ? one start address and transfer size. in linked-list mode , the powerspan ii loads its dma registers from a linked-list of ?command packets?. the packets are essentially pre-pr ogrammed register contents for a powerspan ii dma channel. in the single pci powerspan ii, the pci-2 specific dma bits must not be programmed. dma transfers must not be directed to the pci-2 interface.
4. dma 114 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 4.2 dma register description the dma registers are the same for each dma channel. dma registers are described in table 26 . the registers for dma1 begin at offset 0x300 and their organization in powerspan ii register space is described in ?register descriptions? on page 235 . 4.2.1 source and d estination addresses the lower three bits of dma destin ation address register are taken directly from the lower three bits of the source address register. this enforces 8-byte alignment of the starting source and destination addresses. the source and destination address regi sters are part of the co mmand packet contents ( ?linked-list mode dma operation? on page 120 ). table 26: dma register description register register descripti on and operation dmax_src_addr the source addr ess register can be programmed for an address on any one of the three powerspan ii buses. this register can be programmed in direct mode or automatically loaded in linked-list mode. writing to this register while the dma is in operation has no effect. while the dma is active, this register provides the current status of the source address. this address is byte-aligned. dmax_dst_addr the destination a ddress register can be programmed for an address on any one of the three powerspan ii buses ? even the same bus as that used for the source address. this register can be programmed in direct mode or automatically loaded in linked-list mode. writing to this register while the dma is in operation has no effect. while the dma is active, this register provides the status of the current destination address. this address is byte-aligned. the lower bits on the destination address are the same as the lower bits on the source address. dmax_tcr the dma transfer control register specifies the source and destination buses, the endian conversion mode of a transfer involving the processor bus and a pci bus (see ?endian mapping? on page 177 ), and specifies the byte count from any remaining direct mode operation. dmax_cpp the dma command packet pointer register specifies the 32-byte aligned address of the next command packet in the linked-list. this is programmed by powerspan ii as it loads a command packet. there is a last flag in this register to indicate the end of the linked-list. dmax_gcsr the dma general control and status register controls dma activity, reflects operational status and enables dma-specific interrupts (see table 27 ) dmax_attr the dma attributes register controls the transfer type and cache-specific behavior of processor bus transactions. it also selects the command packet port. most dma channel registers are locked against any changes by th e user while the channel is active. however, both the stop request (sto p_req) and halt requ est (halt_req) bits, in the ?dma x general control and st atus register? on page 314 , are not locked.
4. dma 115 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the starting byte address on the source port is specified in ?dma x source address register? on page 309 . the starting byte address on the destination port is specified in ?dma x destination address register? on page 310 . 4.2.2 transfer control register the ?dma x transfer control register? on page 311 details the programming options for this register. it controls the direction of the transfer, the endi an conversion between the processor bus and the pci bus and specifies the transfer byte count. note th at the maximum byte count is 16 mbytes. the dma transfer control register is part of the command packet contents ( ?linked-list mode dma operation? on page 120 ). 4.2.3 command packet addressing the ?dma x command packet poin ter register? on page 313 specifies the address for the command packets in linked-list mode. see ?linked-list mode dma operation? on page 120 for more details on command packet processing. 4.2.4 address retry the address retry enable (artry_en) bit in the ?processor bus miscellaneous control and status register? on page 304 controls powerspan ii?s assertion of pb_artry_ during the servicing of transactions. when the artry_en bit is set to 0, the pb slave is disabled from generating address retries. 4.2.4.1 dma addresses and retries if a powerspan ii dma transaction is retried enough times the its retr y counter may expire. when the retry timer expires, the dma transaction does not try to restart the transaction at the original address; it jumps the address. the new address starts at th e nearest address boundary. the nearest address boundary depends on the value pr ogrammed in the dbs field (see ?dma x general control and status register? on page 314 ). for example, the nearest address boun dary for an incremented address when the dma block size is set to 128 by tes is 0x80. in this case, the eq uation for the incremented address value is: original address + 0x80. by advancing the address, powe rspan ii provides a method to step -out of the error condition. in the single pci powerspan ii, the pci-2 specific dma bits must not be programmed. dma transfers must not be directed to the pci-2 interface.
4. dma 116 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 4.2.5 general dma control and status the ?dma x general control and status register? on page 314 is not part of the command packet contents and is set up prior to any dma operation (direct or linked-list mode ). the contents of the dma general control and status register are described in table 27 below. table 27: programming model for dma general control and status register bits type description default setting go write 1 to set initiates dma activity clear chain r/w enables the linked-list mode of operation. disabled stop_req write 1 to set stops dma operation after the internally buffered data is written out to the destination bus. clear halt_req write 1 to set halts dma operation after the completion of the current command packet. clear dact r provides status of dma activity (active or inactive). clear dbs[1:0] r/w controls the byte size of dma transactions when dbs_en is set to 1. clear dbs_en r/w enables byte size control of transactions generated by the dma channel. transaction size is based on the setting of the dbs field. clear off r/w dma channel off counter (number of pb clocks) controls the number of processor clocks between sequential pb tenures. clear p1_err r/ write 1 to clear a status bit indicating an error has occurred on pci-1. clear p2_err r/ write 1 to clear a status bit indicating an error has occurred on pci-2. disregard this bit with the single pci powerspan ii. clear pb_err r/ write 1 to clear a status bit indicating an error has occurred on the processor bus. clear stop r/ write 1 to clear a status bit indicating if the dma has been stopped (stop_req was set) clear halt r/ write 1 to clear a status bit indicating if the dma has been halted (halt_req was set). clear
4. dma 117 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 4.2.6 processor bus tr ansfer attributes the ?dma x attributes register? on page 317 controls the read and writ e transactions generated by the dma as a processor bus master. the default transfer type generated by the processor bus master is shown in table 28 . the global (pb_gbl_) and cache inhibit (pb_ci_) parameters ar e programmable for each dma in the ?dma x attributes register? on page 317 . assertion of pb_gbl_ during a processor bus master transaction instructs all processors on the bus to snoop the transact ion. control of this parameter enables the user to implement non- coherent accesses in specific areas of memory. assertion of pb_ci_ prohibits external agents fr om caching the transaction. done r/ write 1 to clear a status bit indicating if the dma has been completed its direct mode or linked-list mode. clear p1_err_en r/w enables an interrupt if an error occurs on pci-1. disabled p2_err_en r/w enables an interrupt if an error occurs on pci-2. do not program this bit if using the single pci powerspan ii . disabled pb_err_en r/w enables an interr upt if an error occurs on the processor bus. disabled stop_en r/w enables an interrupt if the dma has been stopped (stop_req bit was set). disabled halt_en r/w enables an interrupt if the dma has been halted (halt_req bit was set). disabled done_en r/w enables an interrupt if the dma completes its direct mode or linked-list mode. disabled table 28: default powerspan ii pb master transfer type pb master transfer pb_tt[0:4] 60x command writes 00010 write with flush reads 01010 read table 27: programming model for dma general control and status register bits type description default setting
4. dma 118 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 4.3 direct mode dma operation in direct mode, the contents fo r all of a dma channel register s are directly programmed into powerspan ii before every dma operation (see table 26 ). this results in hi gher software overhead than in linked-list mode since powerspan ii re gister accesses are required for every dma block transfer. 4.3.1 initializing a di rect mode operation the go bit in the ?dma x general control and status register? on page 314 is used when the following conditions are met: ? the chain bit is zero which in dicates a direct mode operation ? all status bits in the dma general control and status register are clea red, including: p1_err, p2_err, pb_err, stop, halt, done the chain bit and status bits can be properly configured on the same register write which sets the go bit. the dma channel delivers data from the so urce port to the destination port until: ? dma is stopped by setting the stop_req bit ? dma encounters an error on one of the buses ? transfer byte count decrements to zero when the direct mode operation completes the program med transfer, powerspan ii sets the done bit. the operation completes when the transfer byte coun t decrements to zero. th e operation of a direct mode operation is illustrated in figure 17 .
4. dma 119 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 17: direct mode dma transfers program: source and destination addresses transfer size and addresses set go bit await termination of dma normal termination? more transfers required? no yes handle error no yes done ensure status bits are clear
4. dma 120 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 4.3.1.1 direct mode transfer acknowledgment the following registers are updated during a transf er and can be used to monitor status during dma channel activity: ? dma source address (dmax_src_addr) in the ?dma x source address register? on page 309 ? dma destination address (dmax_dst_addr) in the ?dma x destination address register? on page 310 ? byte count (bc[23:0]) field in the ?dma x destination addr ess register? on page 310 . 4.3.1.2 terminating a direct mode transfer the current direct mode transfer can be stop ped by writing 1 to the stop_req bit in the ?dma x general control and status register? on page 314 . when this occurs, the ch annel stops attempting to buffer data from the source bus. when the remainin g buffered source data is written to the destination bus, the stop status bit is set. the channel can be restarted by clearing the stop stat us bit (along with any othe r status bits) and then writing a 1 to the go bit. 4.4 linked-list mode dma operation in linked-list (scatter-gather) mode, powerspan ii steps through a linked series of command packets in external memory. the dma is configured with the starting address of th is list and independently reads command packets and execu tes the transfers specified. due to the pipelined nature of dma channel requ ests, up to 256-bytes ca n be transferred after the user programmed the initial stop request.
4. dma 121 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com each command packet is 32-byte aligned. if the command packets are resident in pci memory, the byte ordering is little-endian. if the command packets are resident in processor bus memory, the byte ordering is big-endian. command packets can reside on any one of the three po werspan ii interfaces. the contents of a command packet are descri bed, with the associat ed dma register, in table 29 . the command packet pointer register (dmax_cpp) contains two elemen ts: the next command packet pointer (ncp[31:5]) and th e last bit. the ncp[31:5] field directs the powerspan ii dma to the next command packet in the linked-list. th e last bit indicates the end of the linked-list. the chaining of the command packets is illustrated in figure 18 . table 29: programming model for the command packet contents register register description and operation dmax_src_addr the source ad dress register can be programmed for an address on any one of the three powerspan ii buses. this register can be programmed in direct mode or automatically loaded in linked-list mode. writing to this register while the dma is in operation has no effect. while the dma is active, this register provides the status on the current source address. this address is byte-aligned. dmax_dst_addr the destinati on address register can be programmed for an address on any one of the three powerspan ii buses (including the same bus as that used for the source address). this register can be programmed in direct mode or automatically loaded in linked-list mode. writing to this register while the dma is in operation has no effect. while the dma is active, this register provides the status on the current destination address. this address is byte-aligned. the lower bits on the destination address are the same as the lower bits on the source address. dmax_tcr the dma transfer control register specifies the source and destination buses, the endian conversion mode of a transfer involving the processor bus and a pci bus (see ?endian mapping? on page 177 ), and specifies the byte count from any remaining direct mode operation. dmax_cpp the dma command packet pointer register specifies the 32-byte aligned address of the next command packet in the linked-list. this is programmed by powerspan ii as it loads a command packet. there is a last flag in this register to indicate the end of the linked-list. dmax_attr the dma attributes register specifies to the channel the location of the linked-list port.
4. dma 122 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 18: dma command packet linked-list 4.4.1 initializing a linked-list mode transfer a linked-list mode dma transfer is co nfigured using the following steps: 1. set-up the command packet linked-list in memo ry accessible to any one of the powerspan ii?s three ports. the command packet port selection is in dependent of the port selected as the source or destination port. 2. configure dmax_attr pa rameters and dmax_gcsr. 3. set-up the ncp[31:5] field to point to the first command packet. 4. ensure the bc[23:0] field in the dm a transfer control register is 0. 5. clear all status bits in the dma general control and status register. 6. set the go bit. the steps to configure a linked-list mo de dma transfer are illustrated in figure 19 . reserved dmax_src_addr reserved dmax_dst_addr reserved dmax_tcr reserved dmax_cpp reserved dmax_src_addr reserved dmax_dst_addr reserved dmax_tcr reserved dmax_cpp first command packet second command packet 0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c address offset:
4. dma 123 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 19: sequence of operations in a linked-list transfer the dma walks through the linked-list of command packets until it ex ecutes the last packet. when the operation programmed with that last command packet is completed, the dma sets the done bit. the last bit indicates the end of the linked-list. if the linked-list mode is started with a non-zero byte count in the dma transfer control register, a direct mode dma transfer is initiated by powerspa n ii to clear the remaining byte count value. once that direct mode transfer is co mplete, the dma then processes the linked-list pointed to in the dma command packet pointer register. this mechanism allows the restart of a linked-list transfer that has been stopped with the stop_req bit in the ?dma x general control and status register? on page 314 . set go and chain bit await termination of dma normal termination? yes set up linked list in memory space configure dmax_attr done handle error no set dmax_cpp [ncp]
4. dma 124 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 4.4.1.1 terminating linked-list mode linked-list mode is terminated in two ways: setting the stop_req bit or the halt_req bit in the ?dma x general control and status register? on page 314 . when the stop_req bit is set, the dma stops making source port requests. when all outstanding transactions are completed on the destination bus, the stop status bit is set. the channel can be restarted by clearing the stop status bit (along with any other status bits) and then writing a one to the go bit. processing of the current linked-list can also be halted by setting the halt_req bit. if this bit is set, transfers specified by the curren t command packet are completed and then the dma sets the halt status bit. since dmax_cpp contains the address of the next command packet, the channel can be restarted by writing 1 to halt bit (to clear the halt state), the chain bit (to re-initiate the linked-list mode), and the go bit (to re-activate the dma). 4.5 dma interrupts the powerspan ii dma supports a number of interrup t sources for each channel. individual enable and status bits exist for each source. the status and en able bits are contained in the ?dma x general control and status register? on page 314 : see ?interrupt handling? on page 145 for a complete description of the mapping and status bits for each of these interrupt sources. 4.6 dma error handling powerspan ii can encounter external bus errors while mastering th e source, destination or command packet ports on behalf of a dma ch annel. each dma channel provides the following status bits in the ?dma x general control and status register? on page 314 that indicate an error condition occurred during dma bus master activity: ?p1_err ? p2_err ?pb_err table 30: dma channel interrupt sources and enables interrupt source enable bit done done_en p1_err p1_err_en p2_err p2_err_en pb_err pb_err_en halt halt_en stop stop_en
4. dma 125 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com in addition to the reporting provided by a dma channe l, the participating master also reports the error. see ?error handling? on page 157 . 4.6.1 pci error bits the error bits for pci-1 and pc i-2 are set when the correspon ding powerspan ii pci master encounters one of the following conditions while servicing a dma channel: ?master-abort ? target-abort ? maximum retry limit is reached 4.6.2 processor bus error bit the error bit for the processor bus is set if the powerspan ii pb master encounters one of the following conditions while serv icing a dma channel: ? assertion of pb_tea_ ? maximum retry limit is reached 4.6.3 source port errors when an error occurs on the source port, transactio ns initiated by the source port are terminated. any source data buffered in the powerspan ii is writ ten to the destination port and the appropriate dmax_gcsr error bit is set. due to the pipelined nature of dma channel requests , additional source port transaction activity may occur until all outstanding cha nnel requests are completed. 4.6.4 destination port errors when an error occurs on the destination port tran sactions associated with any buffered data are terminated, and the appropriat e dmax_gcsr error bit is set. due to the pipelined nature of dma channel requests , additional destination port transaction activity can occur until all outstanding channel requests are completed. the occurrence of data parity error does not af fect dma channel behavi or but is captured by the appropriate interface.
4. dma 126 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 4.6.5 command port errors when an error occurs on the co mmand port the appropriate dmax_gcsr error bit is set. the dma channel registers are not updated with command packet data. see ?error handling? on page 157 and ?interrupt handling? on page 145 for a full description of error logging support and associated interrupt mapping options. each powerspan ii external port has error l og registers that provide s additional diagnostic information to assist in error recovery. these error log register s indicate when multiple errors occur due to the pipelined nature of dma channel requests.
127 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 5. i 2 c/eeprom the i 2 c (inter-ic) bus is a bi-directional, two-wire se rial data and serial cl ock bus that provides communication links between integrated circuits (i cs) in an embedded applic ation. each device is recognized by a unique address and can operate as either a receiver device (for example, an lcd driver), or a transmitter device (fo r example, eeprom) with the capab ility to both receive and send information. transmitters and receivers can operate in either master or slave mode, depending on whether the ic initiates data transfers. this chapter discusses the followin g topics about the powerspan ii i 2 c/eeprom interface: ? ?power-up configuration? on page 128 ? ?bus master i 2 c transactions? on page 135 ? ?pci vital product data (vpd)? on page 135 5.1 overview powerspan ii has a master only, i 2 c bus compatible interface wh ich supports up to eight i 2 c slave devices. this interface is primarily used by powers pan ii for the initializati on of registers and for reading and writing pci vital product data (vpd). however, powerspan ii also provides a mechanism for processor bus and pci masters to access the i 2 c devices. powerspan ii i 2 c interface supports th e following features: ?i 2 c 7-bit device addressing ? standard mode (up to 100 kbits/s) ? single read/write (random read, byte write) ? sequential read during power-up configuration the interface consists of two pins: i2c_sda and i2c_sclk. i2c_sda is a bidirectional open drain signal for transferring address, control, and data bits. i2c_sclk is the clock output for the i 2 c slave devices. i2c_scl is derived from the processor bus clock. for example, at the maximum processor bus clock (pb_clk) frequency of 100 mhz, the i2c_sclk clock rate is 100 khz. powerspan ii does not support mu ltiple masters on the same i 2 c bus.
5. i2c/eeprom 128 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 5.2 power-up configuration at the end of each powerspan ii reset sequence, the i 2 c interface initiates a sequential read with device select code 0b1010000. if no response is detected, the read is terminated and the eeprom load bit (eload), in the ?reset control and status register? on page 324 (rst_csr), is cleared to indicate the absence of an external eeprom. when an eeprom is not used in the system for initialization, the initialization occurs from the processor bus. once initialization is comple te, the p1_lockout and p2_lockout bits must be cleared in the ?miscellaneous control and st atus register? on page 318 (misc_csr) to enable the host processor to assign memory space. when a eeprom is used in a system, the eeprom device responds and a number of powerspan ii register bits are loaded from the ex ternal device and the eload bit is se t. during this loading process, all accesses to powerspan ii?s external interfaces are retried. 5.2.1 eeprom loading when the reset sequence is init iated by assert ion of po_rst_ ? a power-up reset ? the register loading process is defined by table 31 . the first byte read from th e eeprom defines the loading option and is reflected in the eeprom lo ad option (eload_opt) field, in the ?miscellaneous control and status register? on page 318 , at the conclusion of the loading process. the loading options for eeprom are short loading and long loading. the short load consists of 29 bytes and is designed to provide a powerspan ii configuration to sup port the absence of a processor on the pb interface. the long load is 61 bytes in length and provides additional configuration convenience. the upper 192 bytes of the eeprom are reserved for pci vital product data (see ?pci vital product data (vpd)? on page 135 ). table 31 defines the power-up eeprom load sequence. th e shaded areas indicate registers not visible in the single pci powerspan ii. table 31 assumes pci little-endian bi t ordering. consult the register tables for each of the registers listed in the table to obtain the corresponding powerpc big-endian bit ordering. table 31: power-up eeprom load sequence byte offset bit name description 0x00 7-0 misc_csr[eload_opt] 0b00000001=short load 0b00000010=long load 0b00000100=reserved others=do not load 0x01 7-0 powerspan ii reserved 0x02 7-0 powerspan ii reserved 0x03 7-0 powerspan ii reserved
5. i2c/eeprom 129 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com start of short load 0x04 7-0 powerspan ii reserved 0x05 7-4 powerspan ii reserved 3 p1_csr[bm] pci-1 bus master enable 2 p1_csr[ms] pci-1 memory space enable 1 p2_csr[bm] pci-2 bus master enable 0 p2_csr[ms] pci-2 memory space enable 0x06 7-5 powerspan ii reserved 4 p1_bsi2o[prftch] pci-1 i2o target image prefetch indicator 3 p1_bst0[prftch] pci-1 target image 0 prefetch indicator 2 p1_bst1[prftch] pci-1 target image 1 prefetch indicator 1 p1_bst2[prftch] pci-1 target image 2 prefetch indicator 0 p1_bst3[prftch] pci-1 target image 3 prefetch indicator 0x07 7-0 p1_sid[sid[15:8]] pci-1 subsystem id bits 15-8 0x08 7-0 p1_sid[sid[7:0]] pci-1 subsystem id bits 7-0 0x09 7-0 p1_sid[svid[15: 8]] pci-1 subsystem vendor id bits 15-8 0x0a 7-0 p1_sid[svid[7:0]] pci-1 subsystem vendor id bits 7-0 0x0b 7-2 powerspan ii reserved 1 p1_misc1[int_pin[0]] pci-1 interrupt pin bit 0 0 p2_misc1[int_pin[0]] pci-2 interrupt pin bit 0 table 31: power-up eeprom load sequence byte offset bit name description
5. i2c/eeprom 130 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 0x0c 7-5 powerspan ii reserved 4 p1_misc_csr[bsreg_bar_e n] pci-1 register image base address register enable 3 p1_ti0_ctl[bar_en] pci-1 target image 0 base address register enable 2 p1_ti1_ctl[bar_en] pci-1 target image 1 base address register enable 1 p1_ti2_ctl[bar_en] pci-1 target image 2 base address register enable 0 p1_ti3_ctl[bar_en] pci-1 target image 3 base address register enable 0x0d 7-4 p1_ti0_ctl[bs] pci-1 target image 0 block size 3-0 p1_ti1_ctl[bs] pci-1 target image 1 block size 0x0e 7-4 p1_ti2_ctl[bs] pci-1 target image 2 block size 3-0 p1_ti3_ctl[bs] pci-1 target image 3 block size 0x0f 7 misc_csr[vpd_en] pci vital product data enable 6-4 misc_csr[vpd_cs[2:0]] pci vital product data chip select 3-0 powerspan ii reserved 0x10 7 misc_csr[p1_lockout] pci-1 lockout 6 misc_csr[p2_lockout] pci-2 lockout 5-4 powerspan ii reserved 3 misc_csr[pci_arb_cfg] pci arbiter configuration complete 2 misc_csr[pci_m7] pci arbiter master 7 1 misc_csr[pci_m6] pci arbiter master 6 0 misc_csr[pci_m5] pci arbiter master 5 table 31: power-up eeprom load sequence byte offset bit name description
5. i2c/eeprom 131 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 0x11 7 idr[p2_hw_dir] p2_inta direction 6 idr[p1_hw_dir] p1_inta direction 5 idr[int5_hw_dir] int [5] direction 4 idr[int4_hw_dir] int [4] direction 3 idr[int3_hw_dir] int [3] direction 2 idr[int2_hw_dir] int [2] direction 1 idr[int1_hw_dir] int [1] direction 0 idr[int0_hw_dir] int [0] direction 0x12 7-6 powerspan ii reserved 5 pci_i2o_ctl[bar_en] pci i 2 o target image base address register enable 4 powerspan ii reserved 3-0 pci_i2o_ctl[bs] pci i 2 o target image block size 0x13 7-5 powerspan ii reserved 4 p2_bsi2o[prftch] pci-2 i2o target image prefetch indicator 3 p2_bst0[prftch] pci-2 target image 0 prefetch indicator 2 p2_bst1[prftch] pci-2 target image 1 prefetch indicator 1 p2_bst2[prftch] pci-2 target image 2 prefetch indicator 0 p2_bst3[prftch] pci-2 target image 3 prefetch indicator 0x14 7-0 p2_sid[sid[15:8]] pci-2 subsystem id bits 15-8 0x15 7-0 p2_sid[sid[7:0]] pci-2 subsystem id bits 7-0 0x16 7-0 p2_sid[svid[15:8]] pci-2 subsystem vendor id bits 15-8 0x17 7-0 p2_sid[svid[7:0]] pci-2 subsystem vendor id bits 7-0 table 31: power-up eeprom load sequence byte offset bit name description
5. i2c/eeprom 132 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 0x18 7-5 powerspan ii reserved 4 p2_misc_csr[bsreg_bar_e n] pci-2 register image base address register enable 3 p2_ti0_ctl[bar_en] pci-2 target image 0 base address register enable 2 p2_ti1_ctl[bar_en] pci-2 target image 1 base address register enable 1 p2_ti2_ctl[bar_en] pci-2 target image 2 base address register enable 0 p2_ti3_ctl[bar_en] pci-2 target image 3 base address register enable 0x19 3-0 p2_ti0_ctl[bs] pci-2 target image 0 block size 3-0 p2_ti1_ctl[bs] pci-2 target image 1 block size 0x1a 3-0 p2_ti2_ctl[bs] pci-2 target image 2 block size 3-0 p2_ti3_ctl[bs] pci-2 target image 3 block size 0x1b-0x1f powerspan ii reserved end of short load, long load continues 0x20 7-0 p1_id[did[15:8]] pci-1 device id bits 15-8 0x21 7-0 p1_id[did[7:0]] pci-1 device id bits 7-0 0x22 7-0 p1_id[vid[15:8]] pci-1 vendor id bits 15-8 0x23 7-0 p1_id[vid[7:0]] pci-1 vendor id bits 7-0 0x24 7-0 p1_class[base] pci-1 base class code 0x25 7-0 p1_class[sub] pci-1 sub class code 0x26 7-0 p1_class[prog] pci-1 programming interface 0x27 7-0 p1_class[rid] pci-1 revision id 0x28 powerspan ii reserved 6 pb_si0_ctl[ta_en] pb slave image 0 translation enable 5 pb_si0_ctl[md_en] pb slave image 0 master decode enable 4-0 pb_si0_ctl[bs] pb slave image 0 block size table 31: power-up eeprom load sequence byte offset bit name description
5. i2c/eeprom 133 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 0x29 7 pb_si0_ctl[mode] pb slave image 0 image select 6 pb_si0_ctl[dest] pb slave image 0 destination 5-0 powerspan ii reserved 0x2a 7 pb_si0_ctl[prkeep] pb slave image 0 image prefetch read keep 6-5 pb_si0_ctl[end] pb slave image 0 image endian conversion 4-3 powerspan ii reserved 2-0 pb_si0_ctl[rd_amt] pb slave image 0 read prefetch amount 0x2b 7-0 pb_si0_taddr[31:24] pb slave image 0 translation address bits 31-24 0x2c 7-0 pb_si0_taddr[23:16] pb slave image 0 translation address bits 23:16 0x2d 7-4 pb_si0_taddr[15:12] pb slave image 0 translation address bits 15-12 3 pb_si0_taddr[m3] pb slave image 0 master 3 select 2 pb_si0_taddr[m2] pb slave image 0 master 2 select 1 pb_si0_taddr[m1] pb slave image 0 master 1 select 0 powerspan ii reserved 0x2e 7-0 pb_si0_baddr[31:24] pb slave image 0 base address bits 31-24 0x2f 7-0 pb_si0_baddr[23:16] pb slave image 0 base address bits 23-16 0x30 7-4 pb_si0_baddr[15:12] pb slave image 0 base address bits 15-12 3-0 powerspan ii reserved 0x31 7-0 pb_reg_addr[31:24] pb slave register image base address bits 31-24 0x32 7-0 pb_reg_addr[23:16] pb slave register image base address bits 23-16 0x33 7-4 pb_reg_addr[15:12] pb slave register image base address bits 15-12 3-2 powerspan ii reserved 0 pb_reg_addr[end] pb slave regi ster image endian conversion 0x34 7-0 p2_id[did[15:8]] pci-2 device id bits 15-8 table 31: power-up eeprom load sequence byte offset bit name description
5. i2c/eeprom 134 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com when the reset sequence is initiated by assertion of pb_rst_, p1_rst# or p2_rst#, the first byte of the eeprom is read to determine the loading sequen ce desired. all bytes for the selected load option are read from the eeprom, but only a subset of po werspan ii registers are updated. this subset is defined by the external reset pin that initiated the reset sequence. only those register bits affected by the active reset pin(s) are upda ted with eeprom contents. see ?register descriptions? on page 235 for more information. 0x35 7-0 p2_id[did[7:0]] pci-2 device id bits 7-0 0x36 7-0 p2_id[vid[15:8]] pci-2 vendor id bits 15-8 0x37 7-0 p2_id[vid[7:0]] pci-2 vendor id bits 7-0 0x38 7-0 p2_class[base] pci-2 base class code 0x39 7-0 p2_class[sub] pci-2 sub class code 0x3a 7-0 p2_class[prog] pci-2 programming interface 0x3b 7-0 p2_class[rid] pci-2 revision id 0x3c-0x3f 7-0 powerspan ii reserved end of load sequence 0x40-0xff 7-0 reserved for pc i vital product data (vpd) when a long eeprom load is executed, the pb slave image 0 is enable d automatically. the img_en bit is set to 1 in the pb_s1_ctl register. table 31: power-up eeprom load sequence byte offset bit name description
5. i2c/eeprom 135 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 5.3 bus master i 2 c transactions i 2 c master reads and writes can be performed from any one of th e powerspan ii?s three interfaces ? pb, pci-1 or pci-2. these i 2 c transactions are gene rated by accessing the ?i2c/eeprom interface control and status register? on page 322 . this register can be used to access eeprom s or perform arbitrary single byte transfers to other i 2 c compatible devices. since the i 2 c interface is a shared resource, software must use a powerspan ii register semaphore, semax, to acquire exclusive access to interface before initiating transactions with i2c_ csr. the i2c_csr register contains the following fields: ? eeprom address (addr): the 8-bit eeprom addre ss specifies the address for byte writes and random reads. ? data (data): the 8-bit data field is the so urce for writes and destination for reads. ? device code (dev_code): device code is the 4-bit field th at specifies the i 2 c device type. the default is 1010b which is the code for eeproms. ? chip select (cs): chip se lect is the 3-bit field use to select one of th e eight slaves on the i 2 c bus. the device code and chip select fields together form the i 2 c 7-bit device address. ? read/write (rw) ? active (act): when the active bit is set, a transfer is in progress and the register is in read-only mode. after performing a write or read access, the us er must poll the active bit until it is negated before performing other transfers. the active bit is also assert ed during power-up eeprom load and when a pci vital product data transfer is in progress. ? error (err): if the powerspan ii is unable to complete an i 2 c access, the err bit is set when the act is negated. the err bit must be cl eared before attempting another access. 5.4 pci vital product data (vpd) vital product data (vpd) is the information that uniquely defines items such as the hardware, software, and microcode elements of a system. vpd also provides a mechanism for stor ing information such as performance and failure data on a device. vpd resides in a local storage device. powerspan ii supports vpd through the serial eeprom. if an external eeprom is not used, the vpd feature is disabled. there are four bits in table 31 associated with pci vital product data: vpd_en and vpd_cs[2:0]. these bits may also be programmed in the ?miscellaneous control and st atus register? on page 318 . when vpd_en is set, powerspan ii supports pci vital product data through the vpd capabilities registers in the pci configuration space of the designated primary pci interface (see ?primary pci? on page 31 ). the vpd may be located in two differen t places: the upper 192 bytes of the first eeprom (vpd_cs=000) or the entire 256 bytes of a second eeprom with chip select vpd_cs. the vpd enable and vpd chip select fields in the ?miscellaneous control a nd status register? on page 318 are initialized as part of th e short load post reset sequence.
5. i2c/eeprom 136 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com if vpd is located in the first eeprom, the first byte is located at offset 0x40. on every vpd transfer, powerspan ii adds the offset 0x40 to the address in the p1_vpdc or p2_vpdc register. if vpd is not located in the first eeprom, then the address in th e p1_vpdc or p2_vpdc regi ster is used directly as the 8 bit eeprom address. accesses to vital product data in external eeprom is performed in the manner described in ?bus master i 2 c transactions? on page 135 . the bit ordering of the data returned from eeprom in the ?pci-1 vital product data register? on page 267 can be addressed according to litt le-endian or big-en dian conventions. see the bit ordering info rmation in the register table to obtain the necessary bit ordering information.
137 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 6. arbitration arbitration is a process used by mult i-drop bus protocols, such as pci, to support read and write access on a peripheral bus. a bus arbiter is a logic modu le that controls access to the bus by the devices residing on it. for example, when a device requires access to the bus it sends a request si gnal to the bus arbiter. if the bus is not active, the arbiter grants th e device access; otherwise, the device must continue to request access until it is successful in obtaining the bus. this chapter discusses the follow ing topics about powerspan ii?s processor bus and pci arbitration capabilities: ? ?pci interface arbitration? on page 137 ? ?processor bus arbitration? on page 141 6.1 overview powerspan ii has three arbiters. there is an arbiter on each pci interface: pci-1 and pci-2. there is also one arbiter for the processor bus interface. 6.2 pci interface arbitration each powerspan ii pci interface supports a pci centra l arbiter. each arbiter has dedicated support for the powerspan ii pci master ? with internal request an d grant signaling and up to four external pci masters. powerspan ii provides external pins to sup port three additional external pci masters ? pci_req[7:5]#/pci_gnt[7:5]#. pairs of these a dditional arbitration pins can be individually assigned to the pci-1 arbite r or the pci-2 arbiter (see figure 20 ). assignment of these pins is accomplished by initializing the pci arbiter master (pci_mx) bits and pci ar biter pins configuration (pci_arb_cfg) bit in the ?miscellaneous control and status register? on page 318 . these bits can be configured either throug h eeprom load at reset (see ?i2c/eeprom? on page 127 ) or direct powerspan ii register access. requests on pci_req#[7 :5] are ignored until thes e bits are initialized. signals pci_req[7:5]# / pci_gnt[7:5]# operate at a maximum of 33 mhz.
6. arbitration 138 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 20: assignment of additional bus requesters with pci arbiters 6.2.1 arbitration levels the powerspan ii pci arbiter implements a fairness al gorithm in order to prevent deadlocks. there are two priority levels signed to the pci ma ster agents. fairness is defined by the pci 2.2 specification as an algorithm that grants all potential pci masters access to the bus, independent of other requests. 6.2.1.1 high and low priority pci agents there are two priority levels assigned to the pci ma ster agents: high priority and low priority. each priority level performs a round-ro bin arbitration algorithm among th e pci masters assigned to each level. for example, all the pci mast ers assigned to the lower priority level represent one entry in the higher priority round-robin arbitration. for every turn of the high priority ro und-robin arbitration, high priority pci masters asserting px_req# are granted access to the pci bus. at the same time, only one lower priority level pci master asserting px_req# is granted access to the pci bus. arbitration on powerspan ii is hidden. hidden arbitr ation means it occurs du ring the previous access so that no pci cycles are consumed due to arbitration ? except when the bus is in an idle state. in the single pci powerspan ii, pci_req#[7 :5]/pci_gnt#[7:5] are assigned to the pci-1 arbiter. pci-1 arbiter p1_gnt[4:1]# p1_req[4:1]# 44 33 pci-2 arbiter 44 p2_gnt[4:1]# p2_req[4:1]# pci_gnt[7:5]# pci_req[7:5]# assignable to either pci-1 or pci-2
6. arbitration 139 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 6.2.1.2 requesting the pci bus when the bus is idle a master requesting the bus ha s 16 clocks from the detection of px_gnt# asserted to drive px_frame# asserted. if the 16 clocks is exce eded, the arbiter assumes the master is unable to drive the bus and re-arbitrates th e bus to another requesting master . pci masters unable to assert px_frame# within 16 clocks of detecting px_gnt# asserted lose their turn to access the pci bus. functioning and non-functioning pci masters a master that does not respond to the px_gnt# sign al in 16 clocks is considered a non-functioning master by the powerspan ii pci x arbiter when the status enable (status_en) bit is set to 1 in the ?pci-1 bus arbiter control register? on page 284 . the status_en bit enables an internal monitor in the powerspan ii pci x arbiter that checks that no pci master waits longer than 16 pci clock cycles before starting a transaction. when a master takes longer than 16 clocks before st arting a transaction, the status bit is set to 1 in the ?pci-1 bus arbiter control register? on page 284 . when the status bit is set to 1 by the powerspan ii pci x arbiter, the powerspan ii arbiter does not include the non-fu nctioning pci master in its arbitration algorithm. when th e bit is set to 0, the operating status of the pci master is considered by the arbiter to be functioning and the pci master is included in the arbitration algorithm used by powerspan ii. when powerspan ii is reset, all ma sters are considered functioning ? the status bit is set to 0. refer to ?bus parking on a non-functioning master? on page 141 for more information on bus parking on a master that is non-functioning. 6.2.1.3 pci master driving the pci bus a pci master accessing the pci bus has extended assertion of px_gnt# by the arbiter if no other masters are attempting to access th e bus. the arbiter keeps px_gnt # asserted for the pci master actively driving the bus. this enables the pci ma ster to extend its pci access beyond the latency timer. the px_gnt# to the driving pci master remains assert ed for the duration of the transaction, regardless of the state of the master?s px_req# signal. the arbi ter does not try to park the bus on another master while the present master is actively driving the bus with px_req# negated. the arbiter negates all px_gnt# lines for all mast ers except the pci master accessing the pci bus if another pci master asserts px_req# to gain the bus. px_gnt# is negated for the duration of the active access. the powerspan ii arbiter updates the arbitration when it de tects px_frame# negated and px_irdy# asserted ? which occurs in the last data phase of the transaction. the arbitration update is designed to minimize the latency to higher priority pci masters which may have asserted their px_req# while the present transaction was active. the arbitration algorithm is illustrated in figure 21 . the pci bus is idle when both px _frame# and px_irdy# are negated.
6. arbitration 140 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 21: arbitration algorithm each powerspan ii pci arbiter is programmable with the corresponding arbiter control register (see ?pci-1 bus arbiter control register? on page 284 ) and enabled through power-up option pci x arbiter enable (pwr up_px_arb_en) (see ?resets, clocks and powe r-up options? on page 167 ). each master has a arbitration level for pci master device x (mx_pri) bit in the ?pci-1 bus arbiter control register? on page 284 (px_arb_ctrl) to determin e its arbitration level. external arbitration when an external arbiter is used, the powerspa n ii pci master uses px_req#[1]/px_gnt#[1] to acquire the bus. master x master y master z level 0 master c level 0 master a master b level 1 arbitration order level 1, level 1, level 1, level 0 for example, if all bus masters assert request: * a, b, c, x * a, b, c, y * a, b, c, z * a, b, c, x
6. arbitration 141 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 6.2.2 bus parking the powerspan ii pci arbiter provid es a flexible address bus parkin g scheme. when no master is requesting the address bus, the pc i arbiter can park on either the: ? last bus master ? specific bus master the bus parking mode is determined by park bi t in the px_arb_ctrl re gister. when specific master mode is selected by setting the park bit to 0, the bm_park[2:0] fiel d selects the specific bus master for bus parking. the park ed master must enable its drivers for the following pci signals: ? ad[31:0] ? px_c/be#[3:0] ?par bus parking does not occur until the pci bus is idle . when a pci master is a ccessing the bus when no px_req# signals are asserted to the powerspan ii pci arbiter, px_gnt# remains asserted to the master until the bus becomes idle. 6.2.2.1 bus parking on a non-functioning master it is possible for powerspan ii to park the bus on a ma ster that is considered non-functioning or to park the bus on the last master that ha s a status that has changed to non-functioning by the status bit is set to 1 in the ?pci-1 bus arbiter control register? on page 284 . refer to ?functioning and non-functioning pci masters? on page 139 for a detailed description of functioning and non-functioning pci masters. when powerspan ii parks the bus on a non-functioning pci master, the powerspan ii pci x arbiter waits for another ma ster to request the bus. once another master request the bus the pci x arbiter then ignores the non-functioning master until the master is considered functioning. the master status is considered functioning after powerspan ii is reset (default setting) or the status bit is cleared. 6.3 processor bus arbitration powerspan ii?s internal processor bus arb iter is enabled through a power-up option (pwrup_pb_arb_en, see ?resets, clocks and power-up options? on page 167 ). when the internal arbiter is enabled, powerspan ii?s pb master uses an internal ar bitration mechanism to acquire the processor bus. when the internal arbiter is disabled an external arbiter is implemented. the pb master uses address bus request (pb_br[1]_), addre ss bus grant (pb_bg[1]_) and data bus grant (pb_dbg[1]_) to gain external bus ownership. powerspan ii?s internal processor bus arbiter sup ports three external processor bus masters and implements internal request and gran t lines for the powerspan ii itself ? four processor bus masters in total. the external masters are enabled with the external master x enable (mx_en) bits in the ?processor bus arbiter cont rol register? on page 307 .
6. arbitration 142 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the processor bus arbiter implements two levels of priority. devices programmed into a specific priority level operate in a round robin fashion. each master has a external master x priority level (mx_pri) bit in the pb_arb_ctrl regi ster to determine its arbitrati on level for the address bus. the arbitration level for each master can be reconfigured during system run-time. 6.3.1 address bus arbitration the pb_bg_ pins change state under the following conditions: ? the assertion of pb_req_ when the bus is idle. ? after the assertion of pb address acknowledge (pb_aack_), bus grant (pb_bg_) changes to the next requesting master or the parked master. some host processors (for example, the powerqui cc ii) and other processor bus agents require the system signal abb_ to qualify ad dress bus grants. the powerspan ii pb master interface does not require abb_ to qualify data bus grants. 6.3.1.1 bus parking the powerspan ii processor bus arbiter provides a flexible address bus pa rking scheme. when no master is requesting th e address bus, the processor bus ar biter can park on either the: ? last bus master ? specific bus master the bus parking mode is determined by the park bit in the pb_arb_ctrl register. when specific master mode is selected (park = 0), the bm_park[1:0] field selects the specific bus master for address parking. 6.3.2 data bus arbitration the arbiter samples pb_tt[3] when pb_ts_ is asserted to generate data bus requests. the arbiter grants the data bus to the current address bus ow ner by asserting one of pb_dbg[1:3]_ signals. the signal is asserted, by default, one clock after pb_ts_. the pb arbiter can be programmed to sample requests two clocks after the pb_t s_ signals is asserted. the ar biter is programmed through the ts_dly bit in the ?processor bus arbiter control register? on page 307 . requesting masters are required to qualify bu s grants before beginning an address tenure. the parked master does not drive any address bus signals until it generates a request to use the address bus. an example application for this feature is some l2 caches hold the br_ signal after the ts_ signal starts. the powerspan ii arbiter could see th is as a valid request and give the bus to the l2 cache when the bus was not requested. this bit delays when the pb arbiter samples the signal so a false bus request is not granted.
6. arbitration 143 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the current data bus grant is negated when the requesting master has qualified the grant. some host processors (for example, the powerqui cc ii) and other processor bus agents require the system signal dbb_ to qualify data bus grants. the powerspan ii pb master does not require dbb_ to qualify data bus grants. 6.3.2.1 qualifying data bus grant some processors, speci fically the powerpc 7400, must have the da ta bus grant qualified by the arbiter before it is issued to the master. powerspan ii, by default, does not qualify the data bus grant by the powerspan ii pb arbiter and requires that the requesting master qual ify bus grants before beginning an data tenure. the powerspan ii pb arbiter can be programmed to qua lify data bus grants be fore issuing them by setting the 7400_mode bit in the ?reset control and status register? on page 324 . when the 7400_mode bit is set to 1, the pb arbiter qualifies data bus grants before issuing them to a processor bus master. when the 7400_mode bit is disabled (default setting) th e pb arbiter issues a data bus grant to the processor bus master and expects that the processor bus master the at receives the grant qualifies the grant. the 7400_mode bit is a power-up option. 6.3.3 address only cycles the arbiter supports address only cycles. if transfer type (pb_tt[3]) is sampled low during pb_ts_, the arbiter does not grant the data bus. the use of pb_tt[3] as a data bus request means that the powerspan ii pb arbiter does not support the processor bus instructions eciwx and ecowx. 6.3.4 powerspan ii arbi ter and system boot system boot from the pci bus can be selected by conf iguring the processor bus arbiter at power-up to ignore all external requests on pb_br[3:1]_. this allows an external pci ma ster, with the powerspan ii pb master, to configure the host processor memory controller and load boot code before enabling recognition of request s on pb_br[3:1]_. alternatively, at power-up the processor bus arbi ter can be configured to recognize requests on pb_br[1]_ and ignore requests on pb_br[3:2]_. in this case the processor connected to pb_br[1]_ can enable recognition of requests from other ma sters when its system configuration tasks are complete. the powerspan ii processor bus arbiter controls system boot with the m3_en, m2_en and m1_en bits in the ?pci-1 bus arbiter control register? on page 284 (pb_arb_ctrl), as well as the power-up option pwrup_boot. requesting masters are required to qualify bus grants before beginning an data tenure.
6. arbitration 144 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the default value of these mx_en bits in the pb_arb_ctrl register are set using the pwrup_boot option shown in table 32 . when pwrup_boot is select ed to boot from pci, both px_lockout bits in the misc_csr register are cl eared automatically, even if an eeprom is not present. the processor bus arbiter does not ha ve to be enabled to select eith er pci or processor bus boot. the pwrup_boot option sets the m 1_en bit in the pb_arb_ctl re gister and the p1_lockout and p2_lockout bits in the misc_csr register . setting the px_lockout bits means any configuration cycles for powers pan ii on the pci bus are retrie d until the px_lockout bits are cleared from the processor bus or the eeprom. when pci_boot is se t to 1 (boot is from pci) the px_lockout bits are not set for more information on power-up op tions and boot selection, refer to ?powerspan ii power-up options? on page 171 . table 32: mx_en default state pwrup_boot selection rst_csr register m1_en m2_en m3_en boot pci pci_boot=1 0 0 0 boot pb pci_boot=0 1 0 0
145 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 7. interrupt handling an interrupt is a signal informing a program that an event (for example, an er ror) has occurred. when a program receives an interrupt signal, it tempor arily suspends normal pr ocessing and diverts the execution of instructions to a sub-routine hand led by an interrupt controller. the controller communicates with the host processo r and the device that initiated the interrupt to determine how to handle the interrupt. this chapter discusses the fo llowing topics about the powerspan ii interrupt features: ? ?interrupt sources? on page 145 ? ?interrupt registers? on page 147 ? ?interrupt pins? on page 153 ? ?mailboxes? on page 154 ? ?doorbells? on page 155 7.1 overview powerspan ii handles interrupts both from normal device operat ion and from exceptions. these interrupts are programmed through cer tain register settings and are signaled through both input and output signal pins. the following sections describes powerspan ii interrupt handling. 7.2 interrupt sources interrupt sources are classified as originating from normal device operation or conditions generated from an exception. these classifications are discus sed in the following sections. 7.2.1 interrupts from normal operations interrupt sources associated wi th normal device operations are: ? eight bidirectional, conf igurable interrupts pins: p1_inta#, p2_inta#, int[5:0]_ ? dma channels (see ?dma interrupts? on page 154 for dma interrupt sources) ? doorbell interrupts (see ?interrupt enable register 0? on page 332 for doorbell interrupt generation) ?mailbox in terrupts (see ?mailbox x register? on page 349 )
7. interrupt handling 146 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 7.2.2 interrupts from transaction exceptions bus transaction exceptions can occur on any one of the powerspan ii interfaces ? pci-1, pci-2 or processor bus (pb) ? because of bus errors, address parity errors , or data parity errors. when an error occurs, powerspan ii tracks the direction of the tran saction through the interr upt enabling and status function. interrupt sources associated with exceptions are: 1. pb interface errors ? pb_p1_err ? pb_p2_err ?pb_a_par ?pb_p1_d_par ?pb_p2_d_par ? pb_p1_retry ? pb_p2_retry ?pb_pb_err ?pb_pb_d_par ?pb_pb_retry 2. pci-1 interface errors ?p1_pb_err ? p1_p2_err ? p1_a_par ? p1_pb_retry ? p1_p2_retry ? p1_p1_err ? p1_p1_retry 3. pci-2 interface errors ?p2_pb_err ? p2_p1_err ? p2_a_par ? p2_pb_retry ? p2_p1_retry ? p2_p2_err ? p2_p2_retry see ?error handling? on page 157 for information on how these interrupts for bus transaction exceptions are associated with error logging functionality.
7. interrupt handling 147 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 7.3 interrupt registers powerspan ii interrupt status an d enabling, as well as messag e passing through mailboxes and doorbells are controlled by the interrupt registers. table 33 provides a description of powerspan ii registers controllin g these functions. table 33: interrupt register description register type register descripti on and operation status the status register bits cover all of the interrupt sources supported powerspan ii and indicate active interrupt sources when set (see ?interrupt status? on page 148 ). with a some exceptions, all bits in these registers are read and cleared by setting (?r/write 1 to clear?) enable the enable register bits cover all of the interrupt sources supported by powerspan ii and allow status bits to assert an external pin (see ?interrupt enable? on page 150 ). with some exceptions, all bits in these registers are read/write. mapping this series of registers allow each interrupt source to be mapped to a specific interrupt output pin. the mapping definitions are provided in ta b l e 3 8 (see ?interrupt mapping? on page 152 ) direction interrupt direction refers to the ability to control the input/output characteristics of the powerspan ii interrupt pins. each pin has a corresponding bit that configures it as either an input-only or an output-only (see ?interrupt pins? on page 153 ). mailbox the mailbox registers are a series of ei ght 32-bit read/write registers available for message passing between powerspan ii interfaces (see ?mailboxes? on page 154 )
7. interrupt handling 148 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 7.3.1 interrupt status when an interrupt source becomes activ e, the relevant status bit is set in one of the interrupt status registers. interrupt st atus is reported through two registers: ?interrupt enable register 0? on page 332 and ?interrupt status re gister 1? on page 329 . interrupt status register 0 provides status for interrupts resulting from normal device operation. this includes i 2 o, dma, hardware, doorbell and mailbox interrupts. a register descript ion for isr0 is provided in table 34 . all status bits ar e clear by default. table 34: register description for interrupt status register 0 bits type description isr1_actv r this bit indicates an active status bit in isr1. this enables software to monitor activity of the other interrupt status register while observing this interrupt status register. i2o_host r indicates to the host that there are outstanding message frame addresses in the outbound post list fifo. i2o_iop r/ write 1 to clear indicates to the iop that there are outstanding message frame addresses in the inbound post list fifo. dmax r/ write 1 to clear status bit is set when dmax generates an interrupt. see ?dma x general control and status register? on page 314 for details of dmax interrupt sources. x_hw r/ write 1 to clear an interrupt is outstanding on an interrupt input (one of eight interrupt pins, see ?interrupt pins? on page 153 ). dbx r/ write 1 to clear set when a doorbell register is written to in the corresponding ier0 bit. mboxx r/ write 1 to clear set when there is a write to a mailbox.
7. interrupt handling 149 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com interrupt status register 1 provides status for interrupts resulting from exceptions occurring during device operation. this in cludes maximum retry errors, bus erro rs, and parity error. a register description for isr1 is provided in table 35 . table 35: register description for interrupt status register 1 bits type description isr0_actv r this bit allows software to monitor activity of the other interrupt status register while observing this interrupt status register. it essentially chains the two registers so both are only read if necessary. pb_x_retry r/ write 1 to clear the powerspan ii pb master interface has detected more than the maximum allowable retries. pb_x_err r/ write 1 to clear the powerspan ii pb interface asserted (as slave) or received (as master) pb_tea_. the pb slave detects illegal conditions, while the pb master receives pb_tea_. pb_a_par r/ write 1 to clear an address parity error was detected on the pb. pb_x_d_par r/ write 1 to clear a data parity error was detected on the pb. p2_x_err r/ write 1 to clear the powerspan ii pci-2 interface detected an error. the corresponding pci control and status register must be checked for the error. p2_a_par r/ write 1 to clear the powerspan ii pci-2 interface detected an address parity error. p2_x_retry r/ write 1 to clear the powerspan ii pci-2 master has detected more than the maximum allowable retries. p1_x_err r/ write 1 to clear the powerspan ii pci-1 interface detected an error. the corresponding pci control and status register must be checked for the error. p1_a_par r/ write 1 to clear the powerspan ii pci-1 interface detected an address parity error. p1_x_retry r/ write 1 to clear the powerspan ii pci-1 master has detected more than the maximum allowable retries.
7. interrupt handling 150 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the description in table 35 groups several bits under one name . for example, p1_x_retry actually corresponds to p1_p2_retry, p1_pb_retry, and p1_p1_retry. powerspan ii has the following conventions: ? for errors detected by a master , powerspan ii has separate repor ting mechanisms for each source interface. for example, if the powerspan ii pci-2 master detects an address parity error on a transaction claimed by the pb slave, the p2 _pb_a_par bit in the isr1 register is set. ? for errors detected by a targ et/slave, powerspan ii has separa te reporting mechanisms for each destination port. for example, if the powerspan ii pb slave detects a data parity error on a transaction destined for an agent connected to the pci-1 external interface, the p1_pb_a_par bit in the isr1 register is set. 7.3.2 interrupt enable each interrupt enable bit allows an active source status bit to assert one of the external interrupt pins. interrupt enabling is contro lled through two registers: ?interrupt enable register 0? on page 332 and ?interrupt status register 1? on page 329 . interrupt enable register 0 enables interrupts resulting from normal device operatio n. this includes i 2 o, dma, hardware, doorbell and mailbox interrupts. a register description for ier0 is in table 36 . all interrupts are di sabled by default. table 36: register description for interrupt enable register 0 bits type description i2o_host_mask r/w masks an interrupt to the host that there are outstanding mfas in the outbound post list fifo. i2o_iop_en r/w enables an interrupt to the iop indicating that there are outstanding mfas in the inbound post list fifo. dmax_en r/w enables the dmax interrupt x_hw_en r/w enables the corresponding hardwar e interrupt source t (one of eight interrupt pins, see ?interrupt pins? on page 153 ). dbx_en write 1 to set sets the corresponding status bit mboxx_en r/w enables the mailbox interrupt source
7. interrupt handling 151 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com interrupt enable register 1 enables interrupts re sulting from errors occurring during the device operation. this includes maximum retry errors, bus errors, and par ity errors. a register description for ier1 is in table 37 . the descriptions in table 35 , table 36 ,and table 37 groups several bits unde r one name. for example, p1_x_retry actually corresponds to p1_p2_retry, p1_pb_retry, and p1_p1_retry. for errors detected by a master, po werspan ii has separate reporting mechanisms for each source port. for example, if the pci-2 master detects an address parity error on a transaction claimed by the pb slave, the p2_pb_a_par bit in the isr1 register is set. for errors detected by a target/slave, powerspan ii has separate reporti ng mechanisms for each destination port. for example, if th e powerspan ii pb slave detects a data parity error on a transaction destined for an agent co nnected to the pci-1 exte rnal interface, the p1_pb_a_par bit in the isr1 register is set. table 37: register description for interrupt enable register 1 bits type description pb_x_retry_en r/w enables interrupt if the powerspan ii pb master has detected more than the maximum allowable retries. pb_x_err_en r/w enables interrupt if the powerspan ii pb interface asserted (as slave) or received (as master) pb_tea_. pb_a_par_en r/w enables interrupt if an address parity error was detected on the pb. pb_x_d_par_en r/w enables interrupt if a data parity error was detected on the pb. p2_x_err_en r/w enables interrupt if the powerspan ii pci-2 interface detected an error. the corresponding pci control and status register must be checked for the error. p2_a_par_en r/w enables interrupt if the powers pan ii pci-2 interface detected an address parity error. p2_x_retry_en r/w enables interrupt if the powe rspan ii pci-2 master has detected more than the maximum allowable retries. p1_x_err_en r/w enables interrupt if the powerspan ii pci-1 interface detected an error. the corresponding pci control and status register must be checked for the error. p1_a_par_en r/w enables interrupt if the powers pan ii pci-1 interface detected an address parity error. p1_x_retry_en r/w enables interrupt if the powe rspan ii pci-1 master has detected more than the maximum allowable retries.
7. interrupt handling 152 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 7.3.3 interrupt mapping the following registers contain mapping bits for powerspan ii interrupt sources: ? imr_mbox (mailbox sources) ? imr_db (doorbell sources) ? imr_dma (dma channel sources) ? imr_hw (external pin sources) ? imr_p1 (pci-1 sources) ? imr_p2 (pci-2 sources) ? imr_pb (processor bus sources) ? imr2_pb (processor bus sources) ? imr_misc (i 2 o sources) each interrupt source contains a th ree bit field in an imr_x regist er. this mapping field determines which external pin to assert when the source is active and enabled. table 38 details the mapping scheme. the shaded area in the table denotes the shaded map field and interrupt pin information apply onl y to the dual pci powerspan ii table 38: mapping definition map field interrupt pin 000 p1_inta # 001 p2_inta # 010 int[0]_ 011 int[1]_ 100 int[2]_ 101 int[3]_ 110 int[4]_ 111 int[5]_
7. interrupt handling 153 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 7.4 interrupt pins powerspan ii has the following interrupt pins: ?p1_inta# ?p2_inta# ? int[5:0]_ pins int[5:0]_ are 5v tolerant an d general purpose interrupt pins. in terrupt pins are active low and, when configured as input, are sampled on three successive processor bus clock edges to ensure appropriate setting of a status bit. each pin is bidirectional, open drain, active low and level sensitive. the input/output character of each interrupt pin is controlled through a corresponding bit in the ?interrupt direction register? on page 347 . each pin can be configured as either an input or output. all pi ns are configured as inputs by default. p1_inta# and p2_inta# are intended to be used with pci interfaces pc i-1 and pci-2. they are electrically pci compliant. to configure pci interface px with interrupt capability, the following register settings are required: ? int_pin = 0x01, in the ?pci-1 miscellaneous 1 register? on page 262 (px_misc1). this setting enables a single function pci device inta# ? px_hw_dir = 0x01, in the ?interrupt direction register? on page 347 (id). px_inta# is configured as an output pin. if the pci interface px does not require interrupt capability, the following register settings are necessary: ? int_pin = 0x00, in the px_misc1 register. this setting enables a single function pci device that is using no interrupts. ? px_inta = user defined, in the id register . px_inta# is used as general purpose pin. powerspan ii provides an eeprom load feature to au tomatically control the interrupt capabilities of pci-1 and pci-2 (see ?i2c/eeprom? on page 127 ).
7. interrupt handling 154 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 7.5 dma interrupts the powerspan ii dma supports a number of interrup t sources for each channel. individual enable and status bits exist for each source. the status and en able bits are contained in the ?dma x general control and status register? on page 314 : the following programming steps route done, halt and stop interrupts on dma channel two onto int[3]_: ? set the dma2_en bit in the ier0 register ? program the dm a2_map bit to 0bx101 in the imr_dma register ? set the done_en, halt_en, stop_en bits in the ?dma x general control and status register? on page 314 (dmax_gcsr) 7.5.1 dma interrupt servicing to service a dma interrupt, the following steps must be taken: ? read ?interrupt enable register 0? on page 332 (isr0) to determine wh ich dma channel caused the interrupt ? read dmax_gcsr to determine whic h dma source caused the interrupt ? service the interrupt ? write 1 to clear dmax_gcsr[ status_bit ] and allow a restart of the dma channel ? write 1 to clear the dmax_en bit in the isr0 register and negate the interrupt signal 7.6 mailboxes powerspan ii provides eight 32-bit general mailbox registers for pa ssing messages between processes. each mailbox has an associated inte rrupt enable and status bit. when enabled, an interrupt is generated whenever there is a write to the mailbox register. table 39: dma channel interrupt sources and enables interrupt source enable bit done done_en p1_err p1_err_en p2_err p2_err_en pb_err pb_err_en halt halt_en stop stop_en
7. interrupt handling 155 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 7.7 doorbells the doorbell interrupts are generated by writing 1 to the corresponding doorbell x enable (dbx_en) bit in the ?interrupt enable register 0? on page 332 . the doorbell interrupt is cleared by writing a 1 to the corresponding doorbell x (dbx) bit in the ?interrupt status register 0? on page 327 .
7. interrupt handling 156 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com
157 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 8. error handling errors occur in a system as a result of parity, bus, or internal problems. in order to handle errors so that they have minimum effects on an application, devices have a logic module called an error handler. the error handler logs data about the error then comm unicates the information to another device (for example, a host processor) that is ca pable of resolving the error condition. this chapter discusses the foll owing topics about powerspan ii?s error handling features: ? ?pb interface errors? on page 158 ? ?pci interface errors? on page 162 ? ?dma errors? on page 166 8.1 overview powerspan ii has error detection, e rror reporting and error recovery mechanisms for each of the major interfaces ? processor bus (pb), pci-1 and pci-2. the master and target/slave of each interface prov ides error detection for transactions where they participate. the types of errors identified are: ? address parity ? data parity ? bus errors (target-abort, mast er-abort, and pb_tea_ assertion) ? maximum retry errors each of powerspan ii?s interfaces has a mechanism fo r reporting detected erro rs to hardware and/or software. the reporting mechanisms include: ? interrupt status bits in the ?interrupt status register 1? on page 329 ? the error is reported through powerspan ii?s interrupt generation mechanisms ? pci standard error reporting mechanisms
8. error handling 158 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com ? error logging registers that capture paramete rs from the transaction that caused the error ? assertion of external bus protocol pins powerspan ii has separate reporti ng mechanisms for each source po rt when errors are detected by a master. for example, if the pc1-2 master detect s a address parity error on a transaction claimed by the pb slave, the p2_pb_a_par bi t in the isr1 register is set. for errors detected by a target /slave, powerspan ii provides se parate reporting tools for each destination port. for example, if the powerspan ii pb slave detects a data parity error on a transaction destined for an agent connected to the pci-1 external interface, the pb_p1_d_par bit in the isr1 is set. each powerspan ii dma channe l provides an additional reporting mechanism (see ?dma errors? on page 166 ). 8.2 pb interface errors the pb master and slave detect erro r conditions while participating in pb transactions. in addition to interrupt status register 1, the pb interface has the followi ng error reporting mechanisms: ? assertion of pb_tea_ ? provided the transfer error acknow ledge enable (tea_en) bit in the ?processor bus miscellaneous contro l and status register? on page 304 (pb_misc_csr) is set to 1 ? capture of specific para meters from the transacti on that caused the error a. ?processor bus error control and status register? on page 302 (pb_errcs) logs: ?pb_tt signals ? pb_tsiz signals b. ?processor bus address error log? on page 303 (pb_aerr) logs: ? pb_a signals
8. error handling 159 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com table 40 itemizes the error cases detect ed and reported by the pb ma ster and the pb slave. error logging in pb_errcs and pb_aerr is triggered for each of the error cases outlined in table 40 . table 40: pb interface errors interface error destinatio n/source conditions reporting pb slave address parity pci-1, pci-2, registers address only, write, read pb_a_par in the isr1 register data parity pci-1, registers write pb_p1_d_par in the isr1 register pci-2 write pb_p2_d_par in the isr1 register illegal access pci-1 (memory) unaligned access in ppc little-endian mode pb_tea if tea_en=1, pb_p1_err in the isr1 register pci-1 (configuration, io, iack) registers unaligned access in ppc little-endian mode, transaction size > 4 bytes or burst pci-2 (memory) unaligned access in ppc little-endian mode pb_tea if tea_en=1, pb_p2_err in the isr1 register pci-2 (configuration, io, iack) unaligned access in ppc little-endian mode, transaction size > 4 bytes or burst propagation of error from destination master pci-1 read pb_tea if tea_en=1 pci-2 read pb_tea if tea_en=1
8. error handling 160 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the shaded row from the pb slave section of table 40 indicates the pb slave asserts pb_tea_ and sets a bit in the isr1 register when an external pb master attempts a register access or a pci-1 configuration, io or iack transaction wi th any of the following characteristics: ? not naturally aligned ? if endian (end) bit in the pb_reg_b addr register is programmed for powerpc little-endian mode ? transfer size, pb_tsiz, indicates a transfer greater than 4 bytes when a powerspan ii pci master is performing a r ead and encounters a target-abort, or generates a master-abort, an error indication is latched. when the address retry enable (artry_en) bit, in the ?processor bus miscellaneous control and status register? on page 304 , is set to 0 the error is immediately signaled by the pb slav e and the transaction terminates. if artry_en is set to 1, the pb slave propagates this error to the initiating the proces sor bus agent when it returns to retrieve the read data it requested. the assertion of the pb_tea_ sign al is controlled with assertion the transfer error acknowledge enable (tea_en) bit in the pb_m isc_csr register. if tea_en is set, the pb slave reports error scenarios as defined in table 40 . if tea_en is cleared, tr ansactions determined to be in error are not forwarded to the intended interface or registers. the appropriate isr1 status bits are set. pb master data parity external pci-1 agent pb to pci-1 dma read pb_p1_d_par in the isr1 register external pci-2 agent pb to pci-2 dma read pb_p2_d_par in the isr1 register dma pb linked-list pb to pb dma read pb_pb_d_par in the isr1 register external agent asserts pb_tea_ external pci-1 agent pb to pci-1 dma pci-1 to pb dma read/write pb_p1_err in the isr1 register external pci-2 agent pb to pci-2 dma pci-2 to pb dma read/write pb_p2_err in the isr1 register dma pb linked-list pb to pb dma pb_pb_err in the isr1 register max retry expires external pci-1 agent pb to pci-1 dma pci-1 to pb dma pb_p1_retry in the isr1 register external pci-2 agent pb to pci-2 dma pci-2 to pb dma pb_p2_retry in the isr1 register table 40: pb interface errors interface error destinatio n/source conditions reporting
8. error handling 161 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the pb slave propagation of pci master-abort for configuration commands is controlled with the master-abort configuration error mapping (mac_t ea) bit in the pb_misc_csr register. when mac_tea is set, the pb slave returns all ones on a pci configuration read which terminates with master-abort. if mac_tea is cleared, the pb slave asserts pb_tea_. the shaded row from the pb master section of table 40 indicates that the pb ma ster sets a bit in the isr1 register if its transaction is terminated wi th pb_tea_. the sources for such a transaction are: ? external pci-1 agent read or write ? dma channel moving data to/from pci-1 a typical interrupt service rout ine for a pb interface error ? as illustrated for in table 40 ? executes the following steps: 1. read isr1 to determine which interface reported the error. 2. read error logs pb_errcs and pb_aerr to obta in diagnostic informat ion if the pb interface reported the error. 3. clear the error status (es) bit in the pb_errcs to enable future error logging. 4. clear the status bit in isr1 ? this negates external interrupt pin. 5. fix the configur ation issue that caused the error. 6. retry the transaction that caused the error. the flow of transactions through the powerspan ii inte rfaces is independent of e rror status bits in isr1 and error status bit in the ?processor bus error control and status register? on page 302 . if powerspan ii detects an error while processing a transa ction, subsequent trans actions are not affected. the transaction response for a pb slave error is as follows: ? address parity: do not claim the transaction ? data parity: transaction proceed s normally to its destination ? illegal access (see table 40 ) the transaction response for a pb master error is as follows: ? data parity on reads: ? transaction proceeds normally back to the source ? correct data parity is calculated inte rnally and propagated back to the source
8. error handling 162 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com ? assertion of pb_tea_, expira tion of max retry counter: ?all writes ? stop the transaction ? purge the entire source transaction from the switching fabric ? error status sent to dma chan nel registers (for dma writes) ?all reads ? stop the transaction ? latch error condition for pr opagation back to source 8.3 pci interface errors in the following discussion px refers to the pci inte rface that detected the e rror and py refers to the alternate pci interface. the px master and target detect error conditions whil e participating in pci bus transactions. in addition to the ?interrupt status re gister 1? on page 329 (isr1), the px interface provides the following reporting mechanisms: ? external signaling of the following signals: ? target-abort ? master-abort ? address parity errors ? data parity errors ? detection of target-abort. ? standard pci error reporting in ?pci-1 control and status register.? on page 251 (px_csr). ? capture of specific para meters from the transacti on that caused the error: ? ?pci-1 bus error control and status register? on page 281 (px_errcs), which logs pci command ? ?pci-1 address error log register? on page 282 (px_aerr), which logs pci address (px_ad) table 41 on page 163 itemizes the error cases detected and repor ted by the px master and the px target. error logging in px_errcs and px_aerr is triggered for each of these error cases
8. error handling 163 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com table 41: pci interface errors interface error destinatio n/source conditions reporting px ta r g e t address parity pb, registers, py writ e, read px_serr if peresp=1 and serr_en=1, s_serr in the px_csr register if peresp=1 and serr_en=1, d_pe in the px_csr register, px_a_par in the isr1 register data parity pb, registers write px_perr if peresp=1, d_pe in the px_csr register, px_pb_err in the isr1 register py write px_perr if peresp=1, d_pe in the px_csr register, px_py_err in the isr1 register propagation of error from destination master pb read target-abort, s_ta in the px_csr register, px_pb_err in the isr1 register py read target-abort, s_ta in the px_csr register, px_py_err in the isr1 register px master data parity external pb agent px-to-pb dma read px_perr if peresp=1, mdp_d in the px_csr register if px_perr, d_pe in the px_csr register, px_pb_err in the isr1 register external py agent px-to-py dma read px_perr if peresp=1, px_csr[mdp_d] if px_perr_, d_pe in the px_csr register, px_py_err in the isr1 register dma px linked-list px-to-px dma read/write px_perr if peresp=1, mdp_d in the px_csr register if px_perr_, d_pe in the px_csr register, px_px_err in the isr1 register external agent generates target-abort external pb agent px-to-pb dma pb-to-px dma read/write r_ta in the px_csr register, px_pb_err in the isr1 register external py agent px-to-py dma py-to-px dma read/write r_ta in the px_csr register, px_py_err in the isr1 register dma px linked-list px-to-px dma r_ta in the px_csr register, px_px_err in the isr1 register
8. error handling 164 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com when the pb master or py master are performing a read and encounter an error condition, an error indication is latched. the px target propagates this error to the initiating px external master when it comes back to acquire the read data it requested. this scenario is indi cated by the shaded row in the px target section of table 41 . the px target signals a target-abort on the bus and sets the px processor bus error (px_pb_err) bit in the ?interrupt status register 1? on page 329 and signaled target-abort (s_ta) bit in the ?pci-1 control and status register.? on page 251 . in this case the powerspan ii pb master or py master and the px target reports the error. the shaded row from the px master section of table 41 indicates that the px master sets the px_pb_err bit in the isr1 register and the r_ta bit in the px_csr register if its transaction terminates with a target-abort. the sources for such a transaction are: ? external pb agent read or write ? dma channel moving data to/from pb the mdp_d bit in the px_csr register is also set for data parity errors detected by an external target during write transactions. this condition was not included in the px master section of table 41 because the master does not detect the error. the assertion of px_perr# is controlled with the parity error response (peresp) bit in the ?pci-1 control and status register.? on page 251 . the assertion of px_serr# is controlled with the peresp bit and serr# enable (serr_en) bit in the px_csr. px master px master generates master-abort external pb agent px-to-pb dma pb-to-px dma read/write r_ma in the px_csr register, px_pb_err in the isr1 register external py agent px-to-py dma py-to-px dma r_ma in the px_csr register, px_py_err in the isr1 register dma px linked-list px-to-px dma r_ma in the px_csr register, px_px_err in the isr1 register px master maximum retry expires external pb agent px-to-pb dma pb to-px dma px_pb_retry in the isr1 register external py agent px-to-py dma py-to-px dma px_py_retry in the isr1 register dma px linked-list px-to-px dma px_px_retry in the isr1 register table 41: pci interface errors interface error destinatio n/source conditions reporting
8. error handling 165 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the user controls the px target propagation of pci master-abort configuration command initiated on py with mac_err. when the master-abort configuration error mapping (mac_err) bit is set in the ?pci-1 miscellaneous control an d status register? on page 283 , the px target returns all ones on a py configuration read that termin ates with master-abort . when the mac_err bi t is cleared, the px target responds with target-abort. a typical interrupt service rout ine for a pb interface error ? as illustrated for in table 41 ? executes the following steps: 1. read isr1 to determine which interface reported the error. 2. if the pci-1 interface reported the error: ? read error logs px_errcs and px_a err to obtain diag nostic information. ? read px_csr to distinguish address parity, da ta parity, target-abort, master-abort scenarios. 3. clear px_errcs[es] to en able future error logging. 4. clear the status bit in isr1. negates external interrupt pin. 5. clear the error bits in px_csr. 6. fix the configur ation issue that caused the error. 7. retry the transaction that caused the error. the flow of transactions through powerspan ii is independent of error status bits in ?interrupt status register 1? on page 329 , error status bits in ?pci-1 control and status register.? on page 251 and the error log status (es) bit in the ?pci-1 bus error control and status register? on page 281 . the transaction response fo r a px target error is: ? address parity: claim and complete as normal ? data parity: transaction proceed s normally to its destination the transaction response fo r a px master error is: ? data parity on reads ? transaction proceeds normally to its source ? correct data parity is calculated inte rnally and propagated back to the source ? detection of target-abort, generation of ma ster-abort, expiration of max retry counter: ?all writes: ? stop the transaction ? purge the entire source transaction from the switching fabric ? dma writes, error status se nt to dma channel registers ?all reads: ? stop the transaction ? latch error condition for pr opagation back to source
8. error handling 166 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 8.4 dma errors a powerspan ii dma channel requires a powerspan ii master to servi ce source activity and a second powerspan ii master to service destination activity. these mast ers provide error detection and reporting services as described in the previous sections. the dm a channel provides the following additional status bits to indicate an error condition on an interface currently in use: ? processor bus error (pb_err) bit in the ?dma x general control and status register? on page 314 (dmax_gcsr) ? pci-1 bus error (p1_err) in the dmax_gcsr register ? pci-2 bus error (p2_err) in the dmax_gcsr register these status bits can be used to cause the assertion of a powe rspan ii interrupt pin according to ?interrupt handling? on page 145 . assume that an error occurred at the pci-1 master using dma-2. a typical interrupt service routine executes the following steps: 1. isr1 read to determine which interface reported the error. 2. if pci-1 reports the error: ? error logs p1_errcs and p1_aerr read to obtain diagnostic information. ? p1_csr read to distinguish address parity, data parity, target abort, master abort scenarios. 3. isr0 read to determine if a dma2 status bit is set. 4. dma2_gcsr read to determine which condition caused the channel to interrupt. 5. the es bit is cleared in the p1_errcs register to enable future error logging. 6. the status bit in isr is cleared ? this negates external interrupt pin. 7. the status bit in p1_csr is cleared. 8. configuration issue that caused the error is corrected. 9. p1_err bit in the dma2_gcsr is cleared to allow dma channel two to restart. 10. dma channel two is restarted.
167 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 9. resets, clocks and power-up options this chapter describes the resets , clocks and power-up options im plemented by powerspan ii. the following topics are discussed: ? ?reset? on page 167 ? ?clocks? on page 170 ? ?power-up options? on page 171 9.1 reset powerspan ii has several inputs to it s reset logic. it also has the capability of propagating the reset to the other side of the bus. 9.1.1 reset pins powerspan ii reset pi ns are listed in table 42 .. all pins indicate a reset co ndition when driven low, ex cept for heal thy# signal. 9.1.1.1 reset direction control pins each bidirectional reset pin (pb_rs t_, p1_rst#, and p2_rst#) has a dedicated direction control pin. the assertion of a reset pin configured as input pr opagates to the other bus re set pins configured as output. powerspan ii has reset capabilities for pci host, adapter and hot swap applications table 42: powerspan ii reset pins pin name direction description po_rst_ input only power-on reset healthy# input only board status (compactpci hot swap) pb_rst_ bidirectional open drain processor bus hard reset p1_rst # tristate bidirectional pci-1 bus reset p2_rst # tristate bidirectional pci-2 bus reset trst_ input only jtag reset
9. resets, clocks and power-up options 168 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the relationship between the reset and direction control pins is defined in table 43 . the dedicated direction control pins must either be pulled up or down. at least one of the bidirectional reset pins must be configured as an input. typically, the bus reset pi n on the bus closest to the system host must be configured as an input. 9.1.1.2 reset response the assertion of an external reset pin elic its a specific respon se from powerspan ii. table 44 defines how various powerspan ii resources ar e affected by active reset pins. table 43: reset direction control pins control pin associated reset pin description pb_rst_dir pb_rst_ direction of pb_rst_ ? when pb_rst_dir = 0, pb_rst_ is an input ? when pb_rst_dir = 1, pb_rst_ is an output p1_rst_dir p1_rst# direction of p1_rst# ? when p1_rst_dir = 0, p1_rst# is an input ? when p1_rst_dir = 1, p1_rst# is an output p2_rst_dir p2_rst# direction of p2_rst# ? when p2_rst_dir = 0, p1_rst# is an input ? when p2_rst_dir = 1, p2_rst# is an output table 44: powerspan ii reset response reset pin powerspan ii resource plls pci-1 registers pci-2 registers pb registers powerspan ii device specific registers finite state machines po_rst_ = 0 yes yes yes yes yes yes healthy# = 1 yes yes yes yes yes yes pb_rst_ = 0 no no no yes yes yes p1_rst # = 0 no yes no no yes yes p2_rst # = 0 no no yes no yes yes
9. resets, clocks and power-up options 169 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com powerspan ii?s response to the assert ion of a bidirectional reset pin is independent of the direction of that pin. powerspan ii?s pb_rst_, p1_rst# and p2_rst# are bidirectional. when they are configured as outputs, they still sense logic lows . if any of these signals sense the logic low on their particular reset signal, the corresponding powerspan ii bus interface is in a reset state. however, the reset does not propagate to other powerspan ii busses when the rese t pin is configured as an input. in order for powerspan ii to propagate the reset another bus, the reset pin must be config ured as an input (see ?reset generation? on page 169 ) powerspan ii?s input reset pins do not require cl ock synchronization - they are asynchronous. the phase locked loops (plls) in powerspan ii are on ly reset by either the assertion of po_rst_ or negation of healthy#. the assertion of po_rst_ or negation of healthy# causes all the powerspan ii resources to be rese t. these resources are not releas ed from reset until all plls are locked (see table 97 on page 396 and table 102 on page 402 , parameter t 103 ). the healthy# pin tristates all of powerspan ii?s output buffers, a nd inhibits all of powerspan ii?s input buffers. see ?compactpci hot swap silicon support? on page 53 for more details on the use of healthy#. the assertion of trst_ resets the jtag controller and configures the bound ary scan register for normal system operation. 9.1.1.3 reset generation each of powerspan ii?s three interf aces have bidirectional re set pins that are used to reset the hardware on the associated bus. powerspan ii assertion of pb_rst_ occurs if pb_rst_dir is pulled high and one of the following occurs: ? po_rst_ asserted ? p1_rst_dir is pulled low and p1_rst# is asserted ? p2_rst_dir is pulled low and p2_rst# is asserted powerspan ii assertion of p1_rst# occurs if p1_r st_dir is pulled high and on of the following occurs: ? po_rst_ asserted ? pb_rst_dir is pulled low and pb_rst# is asserted ? p2_rst_dir is pulled low and p2_rst# is asserted applications that use both healthy# and po_rst_ must assert healthy# before negating po_rst_. (see table 97 on page 396 and table 102 on page 402 , parameter t 101 ) customers must assert trst_ concurrently wi th po_rst_ as part of the power-up reset sequence. if the powerspan ii jtag interface is not used, the trst_ signal must be pulled-down with a 1 kohm resistor.
9. resets, clocks and power-up options 170 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com powerspan ii assertion of p2_rst# occurs if p2_r st_dir is pulled high and on of the following occurs: ? po_rst_ asserted ? pb_rst_dir is pulled low and pb_rst_ is asserted ? p1_rst_dir is pulled low and p1_rst# is asserted the negation of healthy# tristates all powers pan ii output pins, incl uding the reset outputs. powerspan ii reset outputs do not respond immediatel y to the negation of po_rst_ because they are negated once all internal plls are locked. 9.2 clocks each of the powerspan ii external ports has a clock input pin. the pins are: ?pb_clk ?p1_clk ?p2_clk the clock input for each port enab les powerspan ii?s master/target state machines to be synchronized to the external bus. each interface ha s a dedicated pll designed to eliminate clock tree insertion delay. powerspan ii requires the input clock to be at th e specified frequency before the negation of po_rst_ (see table 97 on page 396 and table 102 on page 402 , parameter t 102 ). powerspan ii plls are reset during either the assertion of po_rst_ or the ne gation of healthy#. the plls are not locked until a certain period after the negati on of po_rst_ or healthy# (see table 97 on page 396 and table 102 on page 402 , parameter t 103 ). each pll has a dedicated configur ation pin to indicate the desire d operating frequency range. the following configuration pins are used by the pll: ?pb_fast ? p1_m66en ? p2_m66en the input clocks are not required to maintain spec ific phase relationships. however, there is a limitation on the range of input clock periods. the ratio of the maximum period to minimum period, for all three clock inputs, must be less than four. fo r example, if the period of pb_clk is 10 ns, the periods of p1_clk and p2_clk must be less than, but not equal to, 40 ns. powerspan ii has power-up options for bypassing all three plls. this capabilit y is used for debugging purposes. idt recommends alwa ys enabling the pll.refer to ?power-up options? on page 171 for more information on power-up options. pb_fast, p1_m66en, and p2_m66en are multip lexed signals. they are also used for powerspan ii power-up options (see ?power-up options? on page 171 ).
9. resets, clocks and power-up options 171 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 9.3 power-up options to ensure proper operation, a number of powerspan ii features must be configured by completion of the power-up reset sequence. powerspan ii has th e following modes to configure these power-up options: ? multiplexed system pins mode ? configuration slave mode (only av ailable in a powerquicc ii system) the multiplexed system pins mode multiplexes se veral input pins during the power-up reset sequence to configure power-up options. the multiplexed system pins mode is the default mode for powerspan ii. in the configuration slave mode, the power-up options are latched from pb_d. pb_rstconf_ is asserted by the configuration master during the assertion of pb_rst_. refer to the mpc8260 (powerquicc ii) user manual for a detailed description of configuration master functionality. power-up option status can be conf irmed by reading the reset control and status (rst_csr) register (see ?configuration slave mode? on page 175 for more information). table 45 lists powerspan ii power-up options and directio ns for their configurat ion with powerspan ii system pins and the processor data bus in configuration slave mode. power-up options are not affected by reset events on the pb_rst_, p1_rst# or p2_rst# pins. table 45: powerspan ii power-up options power-up option selection system pin a pb_d pin b rst_csr register pb arbiter enable (pwrup_pb_arb_en) enable pb arbiter pb_fast=1 pb_d[0]=1 pb_arb_en=1 disable pb arbiter pb_fast=0 pb_d[0]=0 pb_arb_en=0 pci-1 arbiter enable (pwrup_p1_arb_en) enable pci-1 arbiter p1_m66en=1 pb_d[1]=1 p1_arb_en=1 disable pci-1 arbiter p1_m66en=0 pb_d[1]=0 p1_arb_en=0 pci-2 arbiter enable (pwrup_p2_arb_en) enable pci-2 arbiter p2_m66en=1 pb_d[2]=1 p2_arb_en=1 disable pci-2 arbiter p2_m66en=0 pb_d[2]=0 p2_arb_en=0 primary pci select (pwrup_pri_pci) pci-1 is primary int[5]_=1 pb_d[3]=0 pri_pci=0 pci-2 is primary int[5]_=0 pb_d[3]=1 pri_pci=1
9. resets, clocks and power-up options 172 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the options pwrup_pb_arb_en, pwrup_p1_arb_en, and pwru p_p2_arb_en are used to select between an external arbiter or a powerspan ii arbiter for each interface. pwrup_pri_pci designates either pci-1 or pci-2 as being co nnected to the primary pci interface segment in the system (see ?primary pci? on page 31 for more details on primary pci interface functionality). when pwrup_p1_r64_en is enabled, the powerspa n ii pci-1 interface dr ives p1_req64# during assertion of p1_rst# to signal the presence of a 32-bit or 64-bit data path to all agents on the pci-1 bus segment. this option must only be enabled when powerspan ii is the central resource in the system. the option pwrup_boot enables the system desi gner to control boot from pci or from the processor bus. whether this feature is enabled or disabled is depende nt on system requirements (refer to ?arbitration? on page 137 for more information). by enabling option pwrup_bypass_en, all plls in the design are bypassed. typically, this option must be disabled (pll in use) in the system. in the single pci powerspan ii, the followi ng power-up options are not configurable: ? pwrup_p2_arb_en ? no pci-2 arbiter pci-1 req64 enable (pwrup_p1_r64_en) disable p1_req64_ int[4]_=1 pb_d[4]=0 p1_r64_en=0 enable p1_req64_ int[4]_=0 pb_d[4]=1 p1_r64_en=1 boot select (pwrup_boot) pb boot int[3]_=1 pb_d[5]=0 pci_boot=0 pci boot int[3]_=0 pb_d[5]=1 pci_boot=1 7400 mode enable (pwrup_7400_mode) disable 7400_mode int[2]_=1 pb_d[6]=0 7400_mode=0 enable 7400_mode int[2]_=0 pb_d[6]=1 7400_mode=1 pll bypass enable (pwrup_bypass_en) disable pll bypass int[1]_=1 pb_d[7]=0 bypass_en=0 enable pll bypass int[1]_=0 pb_d[7]=1 bypass_en=1 a. the information in the system pin column is used when powerspan ii is in multiplexed system pin mode (see page 173 ) b. the information in the pb_d pin column is used when powerspan ii is in configuration slave mode ( page 175 ). table 45: powerspan ii power-up options power-up option selection system pin a pb_d pin b rst_csr register
9. resets, clocks and power-up options 173 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com ? pwrup_pri_pci ? pci-1 is always the primary interface 9.3.1 multiplexed system pin mode powerspan ii multiplexes a number of pins to pr ovide either power-up opt ions or other system application purposes (see table 45 ). the multiplexed sy stem pins mode is the default mode for powerspan ii power-up options. 9.3.1.1 signal timing requirements pwrup_pb_arb_en, pwrup_p1_arb_en, and pw rup_p2_arb_en have multiple purposes: determines the pll frequency range, and the powerspan ii power-up option. during the low to high transition of po_rst_, the following pins are latched by powerspan ii in order to choose the following internal clock pll frequency range: ? pb_fast signal ? high when the pb clock frequency is between 50 mhz and 100 mhz ? low when the pb clock frequency is between 25 mhz and 50 mhz ? p1_m66en signal ? high when the pci-1 clock frequency is 66 mhz ? low when the pci-1 clock frequency is 33 mhz ? p2_m66en signal ? high when the pci-2 clock frequency is 66 mhz ? low when the pci-2 clock frequency is 33 mhz there is a 10 ns minimum input setup time and 10 ns maximum input hold time requirement for latching these frequency range pins for determining the pll range (see table 97 on page 396 and table 102 on page 402 , parameters t 110 and t 111 for more ac timing reset information). the arbiter enable and disable (pwr_pb_arb_ en and pwrup_p1_arb_en) power- up options are sampled continuously 10 ns the negation of po_rst_ until the power-up option is updated by the configuration slave mode settings (this is only true in mpc8260 appli cations). the option is determined by the logic level of pb_fast, p 1_66en, and p2_66en signals through internal combination logic. this means the system can enable/disab le arbiter(s) by cont rolling these frequency range pins? logic level during no rmal system operation after the negation of po_rst_ if the pb_rstconf signal is tied to 1 (it never goes low).
9. resets, clocks and power-up options 174 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 9.3.1.2 signal timing for the remainin g power-up options using to int[5:1] during the low to high transition of po_rst_, the int[5:1] pins are internally latched by powerspan ii in order to choose th e required power-up options (see figure 22 ). there is a 10 ns minimum input setup time and 10 ns maximum input hold time requirement for latching int[5:1] for th e power-up options (see table 97 on page 396 and table 101 on page 401 for more ac timing reset information). after the 10 ns hold time, the int[5:1] signals ar e used as general purpos e interrupt pins. normal operation of these pins (as interrupt pins) requir es external pull-ups. de fault values for power-up options loaded by int[5:1]_ are shown in table 45 . figure 22: powerspan ii power-up waveform tip the logic levels are typically provided by exte rnal transceiver or fpga. when int[5:1] are also used for genera l purpose i/o pins. po_rst_ pb_hreset_ pb_rstconf_ pb_d[0:7] int[5:1]_ pb_fast px_m66en pll frequency selected when po_rst_ is transitioned from low to high muliplexed system pin mode (default) power-up options latched off the interrupt pins selected configuration slave mode power-up options selected and all previously selected options are overwritten 10ns muliplexed system pin mode (default) power-up options for arbiter selection are latched continuously healthy#
9. resets, clocks and power-up options 175 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 9.3.2 configuration slave mode when there is a 60x bus device with the capability to be a configur ation master in a powerspan ii system (for example the powerquicc ii) the co nfiguration slave mode overrides the default power-up option ? the multiplexed system pins mode. the slave mode?s power-up options overwrite the multiplex system pin mode power-up optio ns that were sampled at po_rst_ (see figure 22 ). when the powerquicc ii is the configuration master , it asserts one of the a[0:6] signals when the hreset_ signal is low. refer to the mpc8260 (powerqui cc ii) user manual for a detailed description of configurat ion master f unctionality. powerspan ii acts as a configuration sl ave under the following conditions: ? pb_rstconf_ is connected to one of th e configuration mast er?s a[0:6] lines ? pb_rst_ is connected to the configuration master hreset_ signal ? pb_d is connected to the processor bus data line the configuration slave powe r-up options are configured by pb_d as defined in table 45 . powerspan ii configuration slave mode timing is illustrated in figure 23 . figure 23: powerspan ii configuration slave mode timing the configuration master updates all configurati on slaves for each hreset_ sequence. powerspan ii updates its the same configuration wo rd accordingly after each sequence. 9.3.3 assertion of p1_req64# when powerspan ii is used as the central resource in the system and contro ls both p1_req64# and p1_rst#, the pwrup_p1_req64_en bit must be set to 1 in the ?reset control and status register? on page 324 . however, powerspan ii does not assert p1_req 64# signal until its configuration word is latched. in order to meet this re quirement, powerspan ii must not be th e last four configuration slaves (powerquicc ii can support up to seven extern al configuration slaves ). by meeting these requirements, powerspan ii ensures that the timing parameters for a 64-bit data width are satisfied. power-up options configured pb_d[0:7] configuration word pb_rstconf_ pb_rst_
9. resets, clocks and power-up options 176 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com
177 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 10. endian mapping big-endian refers to a method of formatting data where address 0 (o r the smallest address referencing to the data) points to the most significant byte of the data. little-endian refers to a method of formatting data where address 0 (o r the smallest address referencing the data) points to the least significant byte of the data. data in a system must be consistent; that is, the system must be entirely big-endian or little-endian. this chapter describes th e endian mapping system used in po werspan ii. the following topics are discussed: ? ?conventions? on page 177 ? ?processor bus and powerspan ii register transfers? on page 179 ? ?processor bus and pci transfers? on page 183 10.1 overview powerspan ii supports a flexible endian conversion scheme for the following transactions involving the processor bus (pb) interface: ? access of powerspan ii regi sters from the pb interface ? transfers between the processor bus and pci ? both externally initiated and powerspan ii dma initiated 10.2 conventions table 46 illustrates the data bus lanes used to carry each byte of a multi-byte structure on pci. pci stores multi-byte structures with little-endian byte ordering. no endian conversion is performed for trans actions mapped between the two pci interfaces: pci-1 and pci-2. table 46: pci byte lane definitions byte address pci byte lanes ad[2:0] 64-bit transaction 32-bit transaction lane number pins ad[2] lane number pins 000 0 p1_ad[7:0] 0 0 px_ad[7:0]
10. endian mapping 178 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com table 47 illustrates the lanes used to carry each byte of a multi-byte structure on a 64-bit pb interface data bus. powerspan ii supports both big-endian and powerpc li ttle-endian byte ordering . endian selection with powerpc is performed with the pr ocessor register msr[le] and de faults to big-endian. powerpc little-endian mode allows a powerpc and pentium processor to share a data structure in memory. 001 1 p1_ad[15:8] 0 1 px_ad[15:8] 010 2 p1_ad[23:16] 0 2 px_ad[23:16] 011 3 p1_ad[31:24] 0 3 px_ad[31:24] 100 4 p1_ad[39:32] 1 0 px_ad[7:0] 101 5 p1_ad[47:40] 1 1 px_ad[15:8] 110 6 p1_ad[55:48] 1 2 px_ad[23:16] 111 7 p1_ad[63:56] 1 3 px_ad[31:24] table 47: 64-bit pb data bus byte lane definitions byte address processor bus byte lanes pb_a[29:31] lane number powerspan ii pins powerquicc ii pins powerpc 7xx pins 000 0 pb_d[0:7] d[0:7] dh[0:7] 001 1 pb_d[8:15] d[8:15] dh[8:15] 010 2 pb_d[16:23] d[16:23] dh[16:23] 011 3 pb_d[24:31] d[24:31] dh[24:31] 100 4 pb_d[32:39] d[32:39] dl[0:7] 101 5 pb_d[40:47] d[40:47] dl[8:15] 110 6 pb_d[48:55] d[48:55] dl[16:23] 111 7 pb_d[56:63] d[56:63] dl[24:31] table 46: pci byte lane definitions byte address pci byte lanes
10. endian mapping 179 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 10.3 processor bus and powerspan ii register transfers the powerspan ii pb slave supports register acces ses from a powerpc operating in big-endian or powerpc little-endian mode. the endian conversion mode for pr ocessor access to powerspan ii registers is selected by programming the end bit in the ?processor bus register image base address register? on page 295 . the default mode is big-endian, wh ich matches the default mode of the processor bus. powerspan ii registers are little-e ndian structures. the endian co nversion process provided by powerspan ii for processor bus accesses to its register s is designed to preserve the significance of the programmer?s multi-byte structures or scalars. endi an conversion for access to powerspan ii registers from the processor is data invariant. when the processor bus is operating in big-endian mode, the end bit must be set to big-endian mode. in this case, the powerspan ii pb slave maps the processor bus byte lanes to powerspan ii register addresses according to table 48 .
10. endian mapping 180 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com table 48: powerspan ii big-endian pb register accesses transfer size starting address pb_a [29:31] powerpc byte lanes powerspan ii register address a[2] a[1:0] 0 1 2 3 4 5 6 7 11 10 01 00 byte 000 d0 0 d0 001 d1 0 d1 010 d2 0 d2 011 d3 0 d3 100 d4 1 d4 101 d5 1 d5 110 d6 1 d6 111 d7 1 d7 two bytes 000 d0 d1 0 d0 d1 001 d1 d2 0 d1 d2 010 d2 d3 0 d2 d3 100 d4 d5 1 d4 d5 101 d5 d6 1 d5 d6 110 d6 d7 1 d6 d7 tri- byte 000 d0 d1 d2 0 d0 d1 d2 001 d1 d2 d3 0 d1 d2 d3 100 d4 d5 d6 1 d4 d5 d6 101 d5 d6 d7 1 d5 d6 d7 word 000 d0 d1 d2 d3 0 d0 d1 d2 d3 100 d4 d5 d6 d7 1 d4 d5 d6 d7
10. endian mapping 181 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com in powerpc little-endian mode, the processor munges the address and places the scalar on the external byte lanes starting at this modified address. the scalar is still in big-endian or der. this operation is only defined for starting addresses that are a multiple of th e size of the scalar. in powerpc literature, this is referred to as being naturally aligned. the munging performed by the processor is illustrated in table 49 . when the processor bus is operatin g in powerpc little-endian mode, end bit must be set to powerpc little-endian mode. in this case, the pb slave munges the processor bus address, and maps byte lanes to register addresses to preserve the significance of the scalar. tip munging the address makes the address appear to the processor bus th at individual aligned scalars are stored as little-end ian values when they are actuall y stored in big-endian order. they are stored at different by te addresses with a double word. table 49: processor bus address munging transfer size address modification 4 bytes xor with 0b100 2 bytes xor with 0b110 1 byte xor with 0b111
10. endian mapping 182 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the byte lane to register address mapping is shown in table 50 . only munged cases are illustrated. the pb slave asserts pb_tea_ in response to an unalign ed access to a register if the end bit is set for powerpc little-endian mode. a pci transaction is generated by accessing the following registers: ? processor bus configuration cycl e data register (pb_conf_data) ? processor bus to pc i-1 interrupt acknowledge cycle ge neration register (pb_p1_iack) ? processor bus to pc i-2 interrupt acknowledge cycle ge neration register (pb_p2_iack) the endian conversion scheme appl ied for processor bus access to thes e registers is controlled by the end bit, but the endian mapping sche me in this case is described in ?processor bus and pci transfers? on page 183 . table 50: powerspan ii powerpc little-endian pb register accesses transfer size starting address (munged) pb_a [29:31] powerpc byte lanes powerspan ii register address a[2] a[1:0] 0 1 2 3 4 5 6 7 11 10 01 00 byte 000 d0 1 d0 001 d1 1 d1 010 d2 1 d2 011 d3 1 d3 100 d4 0 d4 101 d5 0 d5 110 d6 0 d6 111 d7 0 d7 two bytes 000 d0 d1 1 d0 d1 010 d2 d3 1 d2 d3 100 d4 d5 0 d4 d5 110 d6 d7 0 d6 d7 word 000 d0d1d2d3 1 d0 d1 d2 d3 100 d4d5d6d7 0 d4 d5 d6 d7
10. endian mapping 183 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 10.4 processor bus and pci transfers the following endian conversion mo des are provided for transactions involving the processor bus and a pci interface: ? big-endian (swap or address invariance) ? little-endian (no swap or data invariance) ? powerpc little-endian (no swap and address munge) ? true little-endian (swa p or address invariance) the following powerspan ii register bits are used to control the endian co nversion for transactions involving the pb interface and pci: ? end [1:0] field in the ?pci-1 target image x control register? on page 268 ? end [1:0] field in the ?pci i2o target image control register? on page 352 ? end [1:0] field in the ?processor bus slave image x control register? on page 287 ? end [1:0] field in the ?dma x transfer control register? on page 311 the endian conversion mode of a dma channel can be updated for each direct mode transaction or for each element in a linked-list. the following sections describe each of the endian conversion modes. 10.4.1 big-endian mode when operating in big-endian mo de, powerspan ii uses an addre ss invariant scheme for mapping processor bus byte lanes. in this mode, all elements of a multi-byte structure or scalar appear at the same address in both pci and processor bus spaces , but their relative significance is not preserved. if the processor bus is programmed to be big-endian, powerspan ii big-endian mode must be used for processor bus/pci transactions. powerspan ii byte lane mappings for big- endian mode support are illustrated in table 51 . byte lane number references are defined in table 46 and table 47 .
10. endian mapping 184 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com table 51: powerspan ii big-endian mode byte lane mapping transfer size start address powerpc byte lanes pci byte lanes 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0 byte 000 d0 d0 001 d1 d1 010 d2 d2 011 d3 d3 100 d4 d4 101 d5 d5 110 d6 d6 111 d7 d7 two bytes 000 d0 d1 d1 d0 001 d1d2 d2d1 010 d2 d3 d3 d2 100 d4d5 d5d4 101 d5 d6 d6 d5 110 d6d7d7d6 tri-byte 000 d0d1d2 d2d1d0 001 d1d2d3 d3d2d1 100 d4d5d6 d6d5d4 101 d5d6d7d7d6d5 word 000 d0d1d2d3 d3d2d1d0 100 d4d5d6d7d7d6d5d4 five bytes 000 d0 d1 d2 d3 d4 d4 d3 d2 d1 d0 011 d3d4d5d6d7d7d6d5d4d3 six bytes 000 d0 d1 d2 d3 d4 d5 d5 d4 d3 d2 d1 d0 010 d2d3d4d5d6d7d7d6d5d4d3d2
10. endian mapping 185 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 10.4.2 little-endian mode when operating in little-endian mode, powerspa n ii uses a data invariant scheme for mapping powerpc byte lanes. data invariance preserves the re lative byte significance of a structure in both pci and powerpc spaces, but transl ates the byte addressing. in order to access pci device regi sters from the processor bus in l ittle-endian mode, there are certain addressing rules which must be followed. in powe rspan ii when little-endian mode is selected, no address swapping takes place (refer to table 52 on page 186 ). this means that the msb on the processor bus goes to the msb on pci. however, the msb on processor bus is the low address and msb on pci is the high address. 10.4.2.1 4 byte transactions when performing 4 byte transactions to the pci bus in little-endian mode the intended address must xor the address with 0x4. this creates the addr ess for pci which is used in the transaction. in little-endian mode for 4 byte transfers, the fo llowing changes must be made: ? change a register on pci at offset 0x0 using address 0x4 ? change a register on pci at offset 0x4 using address 0x0 ? change a register on pci at offset 0x8 using address 0xc ? change a register on pci at offset 0xc using address 0x8 these rules enable the transactio ns to reach the intended target s without manual code changes. powerspan ii byte lane mappings for little-endian mode support are illustrated in table 52 on page 186 . seven bytes 000 d0d1d2d3d4d5d6 d6d5d4d3d2d1d0 001 d1d2d3d4d5d6d7d7d6d5d4d3d2d1 double 000 d0d1d2d3d4d5d6d7d7d6d5d4d3d2d1d0 table 51: powerspan ii big-endian mode byte lane mapping transfer size start address powerpc byte lanes pci byte lanes 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0
10. endian mapping 186 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com table 52: powerspan ii little-endian mode byte lane mapping transfer size start address powerpc byte lanes pci byte lanes 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0 byte 000 d0 d0 001 d1 d1 010 d2 d2 011 d3 d3 100 d4 d4 101 d5 d5 110 d6 d6 111 d7 d7 two bytes 000 d0 d1 d0 d1 001 d1 d2 d1 d2 010 d2 d3 d2 d3 100 d4 d5 d4 d5 101 d5 d6 d5 d6 110 d6d7 d6d7 tri-byte 000 d0 d1 d2 d0 d1 d2 001 d1 d2 d3 d1 d2 d3 100 d4 d5 d6 d4 d5 d6 101 d5 d6 d7 d5 d6 d7 word 000 d0 d1 d2 d3 d0 d1 d2 d3 100 d4 d5 d6 d7 d4 d5 d6 d7 five bytes 000 d0 d1 d2 d3 d4 d0 d1 d2 d3 d4 011 d3d4d5d6d7 d3d4d5d6d7 six bytes 000 d0 d1 d2 d3 d4 d5 d0 d1 d2 d3 d4 d5 010 d2 d3 d4 d5 d6 d7 d2 d3 d4 d5 d6 d7
10. endian mapping 187 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 10.4.3 powerpc little-endian mode in powerpc little-endian mode, the pb master swaps byte lanes according to table 52 and munges outgoing addresses pb_a[29:31] according to table 49 . address munging does not occur for burst and extended cycles. in powerpc little-endian mode, the pb master is rest ricted to transferring na turally aligne d quantities. external pci masters or the powerspan ii?s dma ch annels can request transactions that are not naturally aligned. the pb master breaks up thes e requests into single byte transactions on the processor bus, with a performance penalty. the pb slave asserts pb_tea_ in re sponse to a transaction that is no t naturally aligned. these cases are as follows: ? pb_tsiz = 3, 5, 6, 7 bytes ? pb_tsiz = 2 bytes and pb_a[31] = 1 for dma transactions between th e processor (60x) bus and the pci-1 bus, the end bit in the ?dma x transfer control register? on page 311 must be set to 11. for all other powerpc little-endian transfers, the end bit must be set to 01. seven bytes 000 d0 d1 d2 d3 d4 d5 d6 d0 d1 d2 d3 d4 d5 d6 001 d1 d2 d3 d4 d5 d6 d7 d1 d2 d3 d4 d5 d6 d7 double 000 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 table 52: powerspan ii little-endian mode byte lane mapping transfer size start address powerpc byte lanes pci byte lanes 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0
10. endian mapping 188 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 10.4.4 true little-endian mode when operating in true little-endian mode, powers pan ii uses a data invariant scheme for mapping powerpc byte lanes. data invariance preserves the re lative byte significance of a structure in both pci and powerpc spaces, but transl ates the byte addressing. in order to access pci device regi sters from the processor bus in tr ue little-endian mode, there are certain addressing rules which must be followed. in powerspan ii wh en true little-endian mode is selected, no address swapping takes place (refer to table 53 ). this means that the msb on the processor bus goes to the msb on pci. however, the msb on processor bus is the low address and msb on pci is the high address. true little-endian mode cannot be used with th e 4 byte read implementation in the powerspan ii design. the mem_io bit must be set to 0 wh en the end field is set to 11. refer to ?reads? on page 41 and ?reads? on page 95 for a detailed explanation of the 4 byte read through the pci interfaces and pb interface. the 4 byte read implementation can be used with the other types of endian conversion.
10. endian mapping 189 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com table 53: powerspan ii true little-endian byte lane mappings transfer size starting address (munged) pb_a [29:31] powerpc byte lanes powerspan ii pci address a[2] a[1:0] 0 1 2 3 4 5 6 7 11 10 01 00 byte 000 d0 0 d0 001 d1 0 d1 010 d2 0 d2 011 d3 0 d3 100 d4 1 d4 101 d5 1 d5 110 d6 1 d6 111 d7 1 d7 two bytes 000 d0 d1 0 d0 d1 010 d2 d3 0 d2 d3 100 d4 d5 1 d4 d5 110 d6 d7 1 d6 d7 tri bytes 000 d0 d1 d2 0 d0 d1 d2 001 d1d2d3 0 d1 d2 d3 100 d4d5d6 1 d4 d5 d6 101 d5d6d7 1 d5 d6 d7 word 000 d0d1d2d3 0 d0 d1 d2 d3 100 d4d5d6d7 1 d4 d5 d6 d7 five bytes 000 d0 d1 d2 d3 d4 0 d0 d1 d2 d3 1d4 011 d3d4d5d6d7 0 d3 1d4d5d6d7
10. endian mapping 190 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com six bytes 000 d0 d1 d2 d3 d4 d5 0 d0 d1 d2 d3 1d4d5 010 d2d3d4d5d6d7 0 d2 d3 1d4d5d6d7 seven bytes 000 d0 d1 d2 d3 d4 d5 d6 0 d0 d1 d2 d3 1d4d5d6 001 d1d2d3d4d5d6d7 0 d1 d2 d3 1d4d5d6d7 double 000 d0 d1 d2 d3 d4 d5 d6 d7 0 d0 d1 d2 d3 1d4d5d6d7 table 53: powerspan ii true little-endian byte lane mappings transfer size starting address (munged) pb_a [29:31] powerpc byte lanes powerspan ii pci address a[2] a[1:0] 0 1 2 3 4 5 6 7 11 10 01 00
191 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 11. signals and pinout this chapter describes the processor bus (pb) interface, single pci powerspan ii and dual pci powerspan ii signals. signals the differ between the single pci powerspan ii and dual pci powerspan ii are identified in the signal ta bles. the following topics are discussed: ? ?signal descript ion? on page 191 11.1 signal description this section organizes the powerspan ii sign als along the following functional groups: ? processor bus ? pci-1 ? pci-2 ? miscellaneous ?test the dual pci powerspan ii contains all five of these signal groupings. the single pci powerspan ii device does no t implement the pci-2 signal group. 11.1.1 signal types signals are classified accord ing to the types defined in table 54 . table 54: signal type definitions signal type signal type definition input standard input only signal. output standard output only signal. tristate output standard tristate output only signal. open drain open drain output that allows multiple devices to share as a wire-or tristate bidirectional tristate input/output signal. bidirectional open drain open drain input/output which allows multiple devices to share as a wire or when it is used as output. all arbitration signals ? req# and gnt# ? must be weakly pulled-up when using the powerspan ii?s arbiters. this is true for all of powerspan ii?s arbiters: processor bus, pci-1 and pci-2.
11. signals and pinout 192 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 11.1.2 processor bus signals this section describes powerspan ii pb interface signals used to in terface to the 60x bus processors. signals in this group are 3.3v lvttl comp atible. the signals ar e not 5v tolerant. table 55 summarizes the signals in this grouping. signal s with electrical characteristics different from the remainder of the group are placed at the end of the table. table 55: processor bus signals pin name pin type reset state recommended termination description pb_aack_ tristate bidirectional hi-z pull-up resistor address acknowledge: a processor bus slave asserts this signal to indicate that it identified the address tenure. assertion of this signal terminates the address tenure. pb_abb_ tristate output hi-z pull-up resistor address bus busy: indicates ownership of the processor address bus. pb_ap[0:3] tristate bidirectional hi-z pull-up resistor address parity: the processor address bus master drives this signal to indicate the parity of the address bus. pb_artry_ tristate bidirectional hi-z pull-up resistor address retry: assertion of this signal indicates that the bus transaction must be retried by the processor bus master. pb_a[0:31] tristate bidirectional hi-z no requirement a address bus: address for the current bus cycle. it is driven by powerspan ii when it is the 603 bus master. at all other times it is an input to powerspan ii. pb_bg[1]_ tristate bidirectional hi-z pull-up resistor address bus grant: this is an input when an external arbiter is used and an output when the internal arbiter is used. as input it is used by an external arbiter to grant the processor address bus to powerspan ii. as output it is used by the internal arbiter to grant the processor address bus to an external bus master. this pin must be weakly pulled high. pb_bg[2:3]_ tristate output hi-z pull-up resistor address bus grant: it is used by the internal arbiter to grant the processor address bus to the external bus masters. these pins must be weakly pulled high.
11. signals and pinout 193 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com pb_br[1]_ tristate bidirectional hi-z pull-up resistor address bus request: this is an output when an external arbiter is used and an input when an internal arbiter is used. as output it indicates that powerspan ii requests the ownership of the processor address bus. as input an external master should assert this signal to request the ownership of the processor address bus from powerspan ii?s internal arbiter. this pin must be weakly pulled high. pb_br[2:3]_ input hi-z pull-up resistor address bus request: these are inputs only. they are used by external masters to request the processor address bus from the internal arbiter. these pins must be weakly pulled high. pb_ci_ tristate output hi-z pull-up resistor cache inhibit: it is used for l2 cache control. it indicates whether the transaction should be cached or not. pb_clk input - - processor bus clock: all devices intended to interface with the bus processor side of the powerspan ii must be synchronized to this clock. the pb_clk can operate up to 100 mhz. pb_dbb_ tristate output hi-z pull-up resistor data bus busy: indicates the ownership of the data bus. the master who owns the processor data bus asserts this signal. table 55: processor bus signals pin name pin type reset state recommended termination description
11. signals and pinout 194 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com pb_dbg[1]_ tristate bidirectional hi-z pull-up resistor data bus grant: this is an input when an external arbiter is used and an output when the internal arbiter is used. as input it is used by an external arbiter to grant the processor data bus to powerspan ii. as output it is used by the internal arbiter to grant the processor data bus to an external bus master. this pin must be weakly pulled high. pb_dbg[2:3]_ tristate output hi-z pull-up resistor data bus grant: this is an output only. it is used by the internal arbiter to grant the processor data bus to external bus masters. these pins must be weakly pulled high. pb_dp[0:7] tristate bidirectional hi-z no requirement a data parity: the processor data bus slave drives on reads, master drives on write to indicate the parity of the data bus. pb_dval_ tristate bidirectional hi-z pull-up resistor data valid: indicates if the data beat is valid on pb_d[0:63]. pb_d[0:63] tristate bidirectional hi-z no requirement a data bus pb_fast input - power-up option pll configuration: if the signal is pulled low, it configures the pb interface pll to operate with input frequencies between 25 and 50 mhz. if the signal is pulled high, it configures the pb interface pll to operate with input frequencies above 50 mhz to a maximum of 100 mhz. pb_gbl_ tristate output hi-z pull-up resistor global: indicates that the transfer is coherent and it should be snooped by bus masters. pb_rstconf_ input (schmitt trigger) -- reset configuration: asserted by powerquicc ii master to indicate to powerspan ii to load power-up options. this pin must be pulled high if the multiplexed system pin mechanism is used to load the power-up options. table 55: processor bus signals pin name pin type reset state recommended termination description
11. signals and pinout 195 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com pb_rst_ bidirectional open drain (schmitt trigger) low (if pb_rst_dir=1, otherwise the signal is an input) pull-up resistor reset: asynchronous active low reset. pb_rst_dir input - power-up option processor bus reset direction pb_ta_ tristate bidirectional hi-z pull-up resistor transfer acknowledge: indicates that a data beat is valid on the data bus. for single beat transfers, it indicates the termination of the transfer. for burst transfers, it will be asserted four times to indicate the transfer of four data beats with the last assertion indicating the termination of the burst transfer. pb_tbst_ tristate bidirectional hi-z pull-up resistor transfer burst: the bus master asserts this pin to indicate that the current transaction is a burst transaction pb_tea_ tristate bidirectional hi-z pull-up resistor transfer error acknowledge: indicates a bus error. pb_tsiz[0:3] tristate bidirectional hi-z pull-down resistor on tsiz[0] b transfer size: indicates the number of bytes to be transferred during a bus cycle. pb_ts_ tristate bidirectional hi-z pull-up resistor transfer start: indicates the beginning of a new address bus tenure. pb_tt[0:4] tristate bidirectional hi-z no requirement a transfer type: the bus master drives these pins to specify the type of the transaction. pb_vdda supply - - pb analog vdd: voltage supply pin to the analog circuits in the pb phase locked loop (nominally 2.5v). pb_dvdd supply - - pb digital vdd: voltage supply pin to the digital circuits in the pb phase locked loop (nominally 2.5v). table 55: processor bus signals pin name pin type reset state recommended termination description
11. signals and pinout 196 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 11.1.3 pci-1 signals this section describes powerspan ii signals used to interface to pc i-1. signals in this group are compatible with both 3v and 5v signaling environments ? as defined by the pci 2.2 specification . table 56 summarizes the signals in this grouping. signal s with electrical characteristics different from the remainder of the group are placed at the end of the table. pb_dvss ground - - pb digital vss: ground pin to the digital circuits in the pb phase locked loop. pb_avss ground - - pb analog vss: ground pin to the digital circuits in the pb phase locked loop. a. pull-up resistors are not required on the processor bus ad dress (pb_a[0:31]) and data (pb_d[0:63]) signals to guarantee functional operation of the powerspan ii. however, adding resistors to the address and data signals minimizes the current drawn by the powerspan ii's tristated buffers when the bus is in an idle condition. the system designer must decide whether to add these resistors to the address and data bus. b. a pull-up resistor must be added to the signal if all the external masters in the system support extended cycles. if any exte rnal master in the system does not support extended cycles, powerspan ii?s tsiz[0] signal must be disconnected and a pull-down resistor must be used on the signal. refer to b. ?typical applications? on page 421 for a description and illustration of this type of system. table 56: pci-1 signals a pin name pin type description p1_ad [63:0] tristate bidirectional pci-1 address/data bus: address and data are multiplexed over these pins providing a 64-bit address/data bus. b p1_ack64# tristate bidirectional pci-1 acknowledge 64-bit transaction: active low signal asserted by a target to indicate its willingness to participate in a 64-bit transaction. driven by the target; sampled by the master. rescinded by the target at the end of the transaction. p1_cbe[7:0]# tristate bidirectional pci-1 bus command and byte enable lines: command and byte enable information is multiplexed over all eight cbe lines. p1_devsel# tristate bidirectional pci-1 device select: an active low indication from an agent that is the target of the current transaction. driven by the target; sampled by the master. rescinded by the target at the end of the transaction. table 55: processor bus signals pin name pin type reset state recommended termination description
11. signals and pinout 197 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com p1_frame# tristate bidirectional pci-1 cycle frame for pci bus: an active low indication from the current bus master of the beginning and end of a transaction. driven by the bus master; sampled by the selected target. rescinded by the bus master at the end of the transaction. p1_gnt[1]# tristate bidirectional pci-1 grant: this is an input when an external arbiter is used and an output when the internal arbiter is used. as input it is used by the external arbiter to grant the bus to powerspan ii. as output it is used by the internal arbiter to grant the bus to an external master. this pin must be weakly pulled high. p1_gnt [4:2]# tristate output pci-1 grant: these are outputs only. they are used by the pci-1 internal arbiter to grant the bus to external masters. pci_gnt [7:5]# tristate output pci-1 grant: these outputs may be driven by the pci-1 or pci-2 internal arbiter to grant the bus to external masters. they are assigned to pci-1 or pci-2 by software. these pins should be weakly pulled high in a system. p1_idsel input pci-1 initialization device select: used as a chip select during configuration read and write transactions. p1_inta# bidirectional open drain pci-1 interrupt a: an active low level sensitive indication of an interrupt. asynchronous to p1_clk. p1_irdy# tristate bidirectional pci-1 initiator ready: an active low indication of the current bus master?s ability to complete the current dataphase. driven by the master; sampled by the selected target. p1_par tristate bidirectional pci-1 parity: carries even parity across p1_ad[31:0] and p1_c/be[3:0]. driven by the master for the address and write dataphases. driven by the target for read dataphases. p1_par64 tristate bidirectional pci-1 parity upper dword: carries even parity across p1_ad[63:32] and p1_cbe[7:4]. driven by the master for address and write dataphases. driven by the target for read dataphases. p1_clk input pci-1 clock: clock input for the pci-1 interface: p1_clk operates between 25 and 66mhz. p1_m66en input pci-1 66 mhz enable: when pulled low, configures the pci-1 pll for operation between 25 and 33 mhz. when pulled high, configures the pci-1 interface pll for operation above 33 mhz to a maximum of 66 mhz. p1_perr# tristate bidirectional pci-1 parity error: an active low indication of a data parity error. driven by the target receiving data. rescinded by that agent at the end of the transaction. p1_req[1]# tristate bidirectional pci-1 bus request: this is an output when an external arbiter is used and an input when the pci-1 internal arbiter is used. as input it is used by an external master to request the bus. as output it is used by powerspan ii to request the bus. this pin must be weakly pulled high. p1_req[4:2]# input pci-1 bus request: these are inputs only. they can be used by external masters to request the bus through the pci-1 arbiter. these pins should be weakly pulled high in a system. table 56: pci-1 signals a pin name pin type description
11. signals and pinout 198 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com pci_req [7:5]# input pci-1 bus request: these inputs are used by external masters to request the bus from the pci-1 or pci-2 arbiter. t hey are assigned to pci-1 or pci-2 by software. these pins must be weakly pulled high in a system. p1_req64# tristate bidirectional pci-1 request 64-bit transfer: an active low indication from the current master of its choice to perform 64-bit transactions. rescinded by the bus master at the end of the transaction. p1_rst# tristate bidirectional pci-1 reset: asynchronous active low reset for pci-1 interface p1_serr# open drain pci-1 system error: an active low indication of address parity error. p1_stop# tristate bidirectional pci-1 stop: an active low indication from the target of its desire to stop the current transition. sampled by the master. rescinded by the target at the end of the transaction. p1_trdy# tristate bidirectional pci-1 target ready: an active low indication of the current target?s ability to complete the dataphase. driven by the target; sampled by the current bus master. rescinded by the target at the end of the transaction. p1_64en# input pci-1 64-bit enable: an active low indication that a compactpci hot swap board is in a 64-bit slot. this signal must be pulled high in a non-hot swap environment. p1_rst_dir input (lvttl) pci-1 bus reset direction p1_vdda supply pci-1 analog vdd: voltage supply pin to the analog circuits in the pci-1 phase locked loop (nominally 2.5v). p1_dvdd supply pci-1 digital vdd: voltage supply pin to the digital circuits in the pci-1 phase locked loop (nominally 2.5v). p1_dvss ground pci-1 digital vss: ground pin to the digital circuits in the pci-1 phase locked loop. p1_avss ground pci-1 analog vss: ground pin to the digital circuits in the pci-1 phase locked loop. a. refer to the pci local bus specification for reset states and recommended terminations of these pci signals. b. to use the powerspan ii dual pci in a 32-bit env ironment, add a pull-up resistor to p1_ad[32:63]. table 56: pci-1 signals a pin name pin type description
11. signals and pinout 199 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 11.1.4 pci-2 signals this section describes powerspan ii signals used to interface to pc i-2. signals in this group are compatible with both 3v and 5v signaling environments ? as defined by the pci 2.2 specification . table 57 below summarizes the signals in this grouping. signals with electrical ch aracteristics different from the remainder of the group are placed at the end of the table. tip these signals are not implemented in the single pci powerspan ii. table 57: pci-2 signals a pin name pin type description p2_ad[31:0] tristate bidirectional pci-2 address/data bus: address and data are multiplexed over these pins providing a 32-bit address/data bus. p2_cbe[3:0]# tristate bidirectional pci-2 bus command and byte enable lines: command and byte enable information is multiplexed over all four cbe lines. p2_devsel# tristate bidirectional pci-2 device select: an active low indication from an agent that is the target of the current transaction. driven by the target; sampled by the master. rescinded by the target at the end of the transaction. p2_frame# tristate bidirectional pci-2 cycle frame for pci bus: an active low indication from the current bus master of the beginning and end of a transaction. driven by the bus master, sampled by the selected target. rescinded by the bus master at the end of the transaction. p2_gnt[1]# tristate bidirectional pci-2 grant: this is an input when an external arbiter is used and an output when the pci-2 internal arbiter is used. as input it is used by the external arbiter to grant the bus to powerspan ii. as output it is used by the pci-2 internal arbiter to grant the bus to an external master. this pin must be weakly pulled high in a system. p2_gnt [4:2]# tristate output pci-2 grant: these are outputs only. they are used by the pci-2 internal arbiter to grant the bus to external masters. these pins must be weakly pulled high in a system. p2_idsel input pci-2 initialization device select: used as a chip select during configuration read and write transactions p2_inta# bidirectional open drain pci -2 interrupt a: an active low level sensitive indication of an interrupt. asynchronous to p2_clk p2_irdy# tristate bidirectional pci-2 initiator ready: an active low indication of the current bus master?s ability to complete the current dataphase. driven by the master; sampled by the selected target. p2_par tristate bidirectional pci-2 parity: carries even parity across p2_ad[31:0] and p2_c/be[3:0]. driven by the master for the address and write dataphases. driven by the target for read dataphases.
11. signals and pinout 200 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com p2_clk input pci-2 clock: clock input for the pci-2 interface. p2_clk operates between 25 and 66mhz. p2_m66en input pci-2 66 mhz enable: when pulled low, configures the pci-2 pll for operation between 25 and 33 mhz. when pulled high, configures the pci-2 interface pll for operation above 33 mhz to a maximum of 66 mhz. p2_perr# tristate bidirectional pci-2 parity error: an active low indication of a data parity error. driven by the target receiving data. rescinded by that agent at the end of the transaction. p2_req[1] tristate bidirectional pci-2 bus request: this is an output when an external arbiter is used and an input when the pci-2 interface internal arbiter is used. as input it is used by an external master to request the bus. as output it is used by powerspan ii to request the bus. this pin must be weakly pulled high. p2_req[4:2] input pci-2 bus request: these are inputs only. they can be used by external masters to request the bus from the pci-2 arbiter. these pins must be weakly pulled high in a system. p2_rst# tristate bidirectional pci-2 reset: asynchronous active low reset for pci-2 interface. p2_serr# open drain pci-2 system error: an active low indication of address parity error. p2_stop# tristate bidirectional pci-2 stop: an active low indication from the target of its desire to stop the current transition. sampled by the master. rescinded by the target at the end of the transaction. p2_trdy# tristate bidirectional pci-2 target ready: an active low indication of the current target?s ability to complete the dataphase. driven by the target; sampled by the current bus master. rescinded by the target at the end of the transaction. p2_rst_dir input (lvttl) pci-2 bus reset direction p2_vdda supply pci-2 analog vdd: voltage supply pin to the analog circuits in the pci-2 phase locked loop (nominally 2.5v). p2_dvdd supply pci-2 digital vdd: voltage supply pin to the digital circuits in the pci-1 phase locked loop (nominally 2.5v). p2_dvss ground pci-2 digital vss: ground pin to the digital circuits in the pci-1 phase locked loop. p2_avss ground pci-2 analog vss: ground pin to the digital circuits in the pci-1 phase locked loop. a. refer to the pci local bus specification for reset states and recommended terminations of these pci signals. table 57: pci-2 signals a pin name pin type description
11. signals and pinout 201 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 11.1.5 miscellaneous signals table 58 below lists powerspan ii signals which are no t necessarily dedicated to the pb, pci-1 or pci-2 interfaces. they have a vari ety of electrical capabilities. table 58: miscellaneous signals pin name pin type reset state recommended termination description int[5:0]_ bidirectional open drain (5v tolerant lvttl) (schmitt trigger) hi-z pull-up resistor interrupt: general purpose interrupt pins enum# open drain output (pci) hi-z pull-up resistor if the application is a system host. otherwise there is no resistor requirement on the signal. system enumeration: used to notify system host that a board has been freshly inserted or extracted from the system. es input (5v tolerant lvttl) (schmitt trigger) - pull-down resistor in non-hot swap environment a ejector switch: indicates the status of hot swap board ejector switch. a logic high value indicates the switch is closed and it is in operation mode. this signal must be pulled low in a non-hot swap environment. led# open drain output (5v tolerant lvttl) low pull-up resistor if the application is a system host. otherwise there is no resistor requirement on the signal. a led: controls the hot swap status led. healthy# input (5 v tolerant lvttl) (schmitt trigger) - pull-down resistor in non-hot swap environment a board healthy: in a hot swap environment, indicates the board is ready to be released from reset and become an active agent on pci. negation of this signal resets all powerspan ii resources, including pll?s. additionally, all powerspan ii outputs are tristated when this pin is negated; inputs and bidirects are inhibited. this signal must be pulled low in a non-hot swap application. po_rst_ input (5 v tolerant lvttl) (schmitt trigger) -- power on reset: assertion of this signal resets all powerspan ii resources, including pll?s.
11. signals and pinout 202 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com i2c_sclk open drain output (5 v tolerant lvttl) hi-z pull-up resistor serial clock: eeprom serial clock. this pin must be pulled high even if an eeprom is not installed on the board. i2c_sda bidirectional open drain (5 v tolerant lvttl) hi-z pull-up resistor serial data: eprom serial data line. this pin must be pulled high even if an eeprom is not installed on the board. vdd core supply - - core vdd: nominally 2.5v vdd i/o supply - - io vdd: nominally 3.3v vss supply - - ground a. refer to the compactpci hot swap specification for information on these signals. table 58: miscellaneous signals pin name pin type reset state recommended termination description
11. signals and pinout 203 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 11.1.6 test signals table 59 lists powerspan ii signals used to support silicon or board level testing. table 59: test signals pin name pin type reset state recommended termination description pi_test1 input internal pull-down resistor pull-down resistor pll test 1: internal pll test signal. this is for internal idt use. pi_test2 input internal pull-down resistor pull-down resistor pll test 2: internal pll test signal. this is for internal idt use. p2_test1 input note: this signal is present in both the single pci powerspan ii and the dual pci powerspan ii. the signal is used for both pci-1 and pci-2 internal testing. internal pull-down resistor pull-down resistor pll test 1: internal pll test signal. this is for internal idt use. p2_test2 input internal pull-down resistor pull-down resistor pll test 2: internal pll test signal. this is for internal idt use. pb_test1 input internal pull-down resistor pull-down resistor pll test 1: internal pll test signal. this is for internal idt use. pb_test2 input internal pull-down resistor pull-down resistor pll test 2: internal pll test signal. this is for internal idt use. tck input (lvttl) hi-z - test clock (jtag): used to clock state information and data into and out of the device during boundary scan. tms input (lvttl) internal pull-up resistor - test mode select (jtag) : used to control the state of the test access port controller tdi input (lvttl) internal pull-up resistor - test data input (jtag): used (in conjunction with tck) to shift data and instructions into the test access port (tap) in a serial bit stream.
11. signals and pinout 204 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com tdo tristate output (lvttl) hi-z - test data output (jtag): used (in conjunction with tck) to shift data and instructions into the test access port (tap) in a serial bit stream. trst_ input (lvttl) (schmitt trigger) internal pull-up resistor pull-down resistor if jtag is not used in the system. otherwise the signal must be toggled with the po_rst_ signal. test reset (jtag): asynchronous reset for the jtag controller. this pin must be asserted during the power-up reset sequence to ensure that the boundary scan register elements are configured for normal system operation. customers must assert trst _concurrently with po_rst_ as part of the power-up reset sequence. te input internal pull-down resistor pull-down resistor test enable: enables manufacturing test. idt recommends that system designers pull this signal low. table 59: test signals pin name pin type reset state recommended termination description
11. signals and pinout 205 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 11.2 dual pci powerspan ii pinout 11.2.1 dual pci powerspan ii 480 hsbga figure 24 illustrates the top, side, and bott om views of the powerspan ii package. table 60: package characteristics feature description package type 480 hsbga package body size 37.5mm jedec specification jedec mo-151 variation bat-1
11. signals and pinout 206 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 24: 480 hsbga 11.2.1.1 package notes 1. all dimensions in mm 2. all dimensions and tolerance conform to ansi y14.5m - 1994 3. conforms to jedec mo-151 variation bat-1 notes: 1. all dimensions in mm. 2. all dimension and tolerances conform to ansi y14.5m-1994. 3. conforms to jedec mo-151 variation bat-1.
11. signals and pinout 207 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 11.2.2 480 hsbga pin information the following table shows the powerspan ii 480 hs bga, 1.27 mm package, pin information. this package is backwards compatible with th e original powerspan?s 480 hpbga device. a1. vss_io g25. vdd25 ac25. vdd25 a2. vss_io g26. p1_ad[9] ac26. p2_test1 a3. pb_a[12] g27. pci_gnt[5]_ ac27. p2_ad[9] a4. pb_a[14] g28. p1_gnt[4]_ ac28. p2_ad[8] a5. pb_a[16] g29. vss_io ac29. vss_io a6. pb_a[18] h1. int[4]_ ad1. pb_d[60] a7. vss_io h2. pb_a[0] ad2. pb_d[52] a8. pb_a[21] h3. pb_a[1] ad3. pb_d[44] a9. pb_a[24] h4. pb_br2_ ad4. jt_trst_ a10. pb_a[27] h5. vdd25 ad5. vdd25 a11. pb_a[31] h25. vdd25 ad25. vdd25 a12. vss_io h26. vss ad26. pci_gnt[7]_ a13. p1_ad[34] h27. p1_ad[12] ad27. p2_ad[12] a14. p1_ad[38] h28. p1_ad[11] ad28. p2_ad[11] a15. p1_ad[41] h29. p1_ad[10] ad29. p2_ad[10] a16. vss_io j1. pb_tt[1] ae1. pb_d[20] a17. p1_ad[48] j2. he althy_ ae2. pb_test1 a18. vss_io j3. pb_tt[2] ae3. pb_d[12] a19. p1_ad[53] j4. pb_tt[3] ae4. pb_bg2_ a20. p1_ad[56] j5. vss ae5. pb_avss a21. p1_ad[59] j25. vss ae6. pb_dvdd a22. p1_ad[62] j26. vss ae7. vdd25 a23. vss_io j27. p1_inta_ ae8. vdd25 a24. p1_cbe[6]_ j28. pci_gnt[6]_ ae9. vss a25. p1_vdda j29. p 1_ad[13] ae10. vdd33 a26. p1_req64_ k1. pb_aack_ ae11. vdd33 a27. p1_ad[0] k2. pb_tt[4] ae12. vdd33 a28. vss_io k3. vss ae13. vss
11. signals and pinout 208 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com a29. vss_io k4. pb_tt[0] ae14. vdd25 b1. vss_io k5. vdd33 ae15. vdd25 b2. vss_io k25. vdd33 ae16. vdd25 b3. pb_a[13] k26. p1_par ae17. vss b4. pb_a[15] k27. p1_cbe[1]_ ae18. vdd33 b5. vss_io k28. p1_ad[15] ae19. vdd33 b6. jt_tms k29. p1_ad[14] ae20. vdd33 b7. p1_rst_dir l1. pb_artry_ ae21. vss b8. pb_a[22] l2. pb_tsiz[3] ae22. vdd25 b9. pb_a[26] l3. pb_bg1_ ae23. vdd25 b10. pb_a[28] l4. pb_br3_ ae24. p2_dvdd b11. pb_ci_ l5. vdd33 ae25. p2_avss b12. p1_ad[32] l25. vdd33 ae26. p2_ad[14] b13. p1_ad[35] l26. p1_trdy_ ae27. p2_ad[13] b14. vss_io l27. p1_devsel_ ae28. p2_test2 b15. p1_ad[42] l28. p 1_stop_ ae29. p2_idsel b16. p1_ad[45] l29. p1_perr_ af1. pb_d[36] b17. p1_ad[49] m1. vss_io af2. pb_d[28] b18. p1_ad[50] m2. pb_t siz[2] af3. int[3]_ b19. p1_ad[54] m3. pb_tsiz[1] af4. pb_dvss b20. p1_ad[57] m4. pb_ts_ af5. pb_clk b21. p1_idsel m5. vdd33 af6. int[1]_ b22. p1_ad[63] m25. vdd33 af7. vss b23. p1_cbe[4]_ m26. p1_cbe[2]_ af8. pb_vdda b24. p1_cbe[7]_ m27. p1_frame_ af9. pb_d[26] b25. p1_test2 m28. p 1_irdy_ af10. pb_d[57] b26. p1_ack64_ m29. vss_io af11. int[0]_ b27. p1_clk n1. pb_ap[3] af12. pb_d[25] b28. vss_io n2. pb_tsiz[0] af13. pb_d[1] b29. vss_io n3. i2c_sclk af14. pb_fast c1. pb_a[11] n4. pb_tbst_ af15. pb_d[24]
11. signals and pinout 209 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com c2. te n5. vss af16. pb_dp[7] c3. vss n25. vss af17. pb_dp[4] c4. jt_tck n26. p1_ad[19] af18. pb_dp[1] c5. pb_a[17] n27. p1_ad[18] af19. p2_rst_ c6. pb_a[19] n28. p1_ad[17] af20. p2_ad[28] c7. pb_dbg2_ n29. p1_ad[16] af21. p2_ad[24] c8. pb_a[23] p1. vss_io af22. vss c9. pb_a[25] p2. pb_ap[1] af23. p2_ad[19] c10. pb_a[29] p3. pb_ap[2] af24. p2_serr_ c11. pb_dbg1_ p4. i2c_sda af25. p2_clk c12. p1_ad[33] p5. vdd25 af26. p2_dvss c13. p1_ad[36] p25. vdd25 af27. p2_inta_ c14. p1_ad[39] p26. p1_ad[22] af28. p2_cbe[1]_ c15. p1_ad[43] p27. p1_ad[21] af29. p2_ad[15] c16. p1_ad[46] p28. vss_io ag1. pb_d[43] c17. p1_serr_ p29. p1_ad[20] ag2. pb_d[35] c18. p1_ad[51] r1. pb_ta_ ag3. vss c19. p1_ad[55] r2. pb _dval_ ag4. int[2]_ c20. p1_req[4]_ r3. pb_tea_ ag5. pb_d[3] c21. p1_ad[60] r4. pb _ap[0] ag6. pb_d[11] c22. p1_par64 r5. vdd25 ag7. pb_d[42] c23. p1_cbe[5]_ r25. vdd25 ag8. pb_d[58] c24. p1_req1_ r26. p1_ad[25] ag9. pb_d[18] c25. p1_gnt1_ r27. p1_ad[24] ag10. pb_abb_ c26. p1_64en_ r28. p1_c be[3]_ ag11. pb_rstconf_ c27. vss r29. p1_ad[23] ag12. pb_d[17] c28. p1_ad[2] t1. pb_d[15] ag13. pb_rst_ c29. p1_ad[1] t2. vss_io ag14. pb_d[40] d1. pb_a[8] t3. pb_d[30] ag15. pb_d[16] d2. pb_a[9] t4. pb_d[39] ag16. pb_dp[6] d3. pb_a[10] t5. vdd25 ag17. pb_dp[3]
11. signals and pinout 210 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com d4. vss t25. vdd25 ag18. pb_dp[0] d5. jt_tdi t26. p1_ad[28] ag19. p2_ad[31] d6. jt_tdo t27. p1_ad[27] ag20. p2_ad[27] d7. pb_a[20] t28. p1_a d[26] ag21. p2_cbe[3]_ d8. vss t29. vss_io ag22. p2_ad[22] d9. vss u1. led_ ag23. p2_ad[18] d10. pb_a[30] u2. pb_d[7] ag24. p2_ad[17] d11. pb_br1_ u3. pb_d [22] ag25. p2_frame_ d12. pb_gbl_ u4. pb_d[47] ag26. p2_req[2]_ d13. p1_ad[37] u5. vss ag27. vss d14. p1_ad[40] u25. vss ag28. p2_req[3]_ d15. p1_ad[44] u26. p1_ad[31] ag29. p2_par d16. p1_ad[47] u27 . vss ah1. vss_io d17. p1_m66en u28. p1_ad[30] ah2. vss_io d18. p1_ad[52] u29. p1_ad[29] ah3. nc d19. p1_req[3]_ v1. vss_io ah4. pb_d[59] d20. p1_ad[58] v2. pb_d[6] ah5. pb_test2 d21. p1_ad[61] v3. pb_d[55] ah6. pb_d[19] d22. enum_ v4. pb_d[23] ah7. pb_d[50] d23. p1_test1 v5. vdd33 ah8. pb_d[34] d24. p1_gnt[2]_ v25. vdd33 ah9. vss_io d25. p1_gnt[3]_ v26. p2 _gnt[3]_ ah10. pb_d[49] d26. p1_dvss v27. p2_gnt[4]_ ah11. pb_d[41] d27. p1_req[2]_ v28. p1_rst_ ah12. pb_d[9] d28. p1_ad[4] v29. vss_io ah13. pb_d[56] d29. p1_ad[3] w1. pb _d[31] ah14. pb_d[32] e1. pb_dbg3_ w2. pb_d[62] ah15. pb_d[8] e2. vss_io w3. pb_d[54] ah16. vss_io e3. pb_a[7] w4. pb_d [46] ah17. pb_dp[2] e4. es w5. vdd33 ah18. pb_d[63] e5. vss w25. vdd33 ah19. p2_ad[30]
11. signals and pinout 211 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com e6. vdd25 w26. p2_ad[0] ah20. p2_ad[26] e7. vdd25 w27. p2_req1_ ah21. vss_io e8. vdd25 w28. p2_gnt1_ ah22. p2_ad[21] e9. vss w29. p2_gnt[2]_ ah23. p2_vdda e10. vdd33 y1. pb_d[21] ah24. p2_ad[16] e11. vdd33 y2. pb_d[38] ah25. vss_io e12. vdd33 y3. pb_d[14] ah26. p2_trdy_ e13. vss y4. pb_d[53] ah27. p2_stop_ e14. vdd25 y5. vdd33 ah28. vss_io e15. vdd25 y25. vdd33 ah29. vss_io e16. vdd25 y26. p2_ad[3] aj1. vss_io e17. vss y27. pci_req[7]_ aj2. vss_io e18. vdd33 y28. p2_ad[2] aj3. pb_d[51] e19. vdd33 y29. p2_ad[1] aj4. pb_d[4] e20. vdd33 aa1. pb_d[37] aj5. pb_dbb_ e21. vss aa2. nc aj6. pb_d[27] e22. vdd25 aa3. pb_d[29] aj7. vss_io e23. vdd25 aa4. vss aj8. pb_d[10] e24. p1_dvdd aa5. vss aj9. pb_d[2] e25. p1_avss aa25. vss aj10. po_rst_ e26. pci_req[5]_ aa26. p2_ad[5] aj11. pb_d[33] e27. p1_ad[6] aa27. p2_ad[4] aj12. vss_io e28. vss_io aa28. vss_io aj13. pb_d[48] e29. p1_ad[5] aa29. p2_m66en aj14. vss_io f1. pb_a[4] ab1. pb_d[5] aj15. pb_d[0] f2. pb_a[5] ab2. pb_d[61] aj16. pb_dp[5] f3. pb_a[6] ab3. pb_d [45] aj17. p2_rst_dir f4. pb_rst_dir ab4. vss aj18. vss_io f5. vdd25 ab5. vdd2 5 aj19. p2_ad[29] f25. vdd25 ab25. vdd25 aj20. p2_ad[25] f26. pci_req[6]_ ab26. p 2_req[4]_ aj21. p2_ad[23]
11. signals and pinout 212 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com f27. p1_ad[8] ab27. p2_c be[0]_ aj22. p2_ad[20] f28. p1_cbe[0]_ ab28. p2_ad[7] aj23. vss_io f29. p1_ad[7] ab29. p 2_ad[6] aj24. p2_cbe[2]_ g1. vss_io ac1. vss_io aj25. p2_irdy_ g2. pb_a[2] ac2. pb_bg3_ aj26. p2_devsel_ g3. pb_a[3] ac3. int[5]_ aj27. p2_perr_ g4. vss ac4. pb_d[13] aj28. vss_io g5. vdd25 ac5. vdd25 aj29. vss_io
11. signals and pinout 213 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 11.2.3 dual pci powerspan ii 504 hsbga figure 25 illustrates the top, side, and bott om views of the powerspan ii package. table 61: package characteristics feature description package type 504 hsbga package body size 27mm jedec specification jedec mo-151 variation aal-1
11. signals and pinout 214 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 25: 504 hsbga 11.2.3.1 package notes 1. all dimensions in mm 2. all dimensions and tolerance conform to ansi y14.5m - 1994 3. conforms to jedec mo-151 variation aal-1 notes: 1. all dimensions in mm. 2. all dimension and tolerances conform to ansi y14.5m-1994. 3. conforms to jedec mo-151 variation aal-1.
11. signals and pinout 215 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 11.2.4 504 hsbga pin information the following table shows the powerspan ii 504 hsbg pin information. a3. jt_tdo h21. vdd25 w21. vdd25 a4. pb_a[19] h22. vdd25 w22. vdd25 a5. jt_tms h23. p1_cbe[0]_ w23. p2_idsel a6. pb_a[21] h24. p1_inta_ w24. p2_ad[5] a7. pb_a[24] h25. p1_a d[15] w25. pci_req[7]_ a8. pb_ci_ h26. p1_cbe[2]_ w26. p2_req[1]_ a9. p1_ad[33] j1. pb_artry_ y1. pb_d[53] a10. p1_ad[32] j2. pb_br3_ y2. pb_d[61] a11. p1_ad[35] j3. int[4]_ y3. pb_d[60] a12. p1_ad[40] j4. pb_br2_ y4. jt_trst_ a13. p1_ad[42] j5. vdd25 y5. pb_d[35] a14. p1_ad[43] j6. vdd25 y6. vdd33 a15. p1_ad[45] j21. vdd25 y21. vdd33 a16. p1_serr_ j22. vdd25 y22. p2_par a17. p1_ad[52] j23. p 1_gnt[4]_ y23. p2_ad[15] a18. p1_ad[53] j24. p 1_ad[13] y24. p2_ad[8] a19. p1_ad[56] j25. p 1_devsel_ y25. p2_ad[6] a20. p1_ad[58] j26. p1_irdy_ y26. p2_m66en a21. p1_ad[61] k1. pb_ts_ aa1. pb_d[45] a22. p1_cbe[7]_ k2. pb _tsiz[3] aa2. int[5]_ a23. p1_gnt[2]_ k3. pb_tt[1] aa3. pb_d[20] a24. p1_ack64_ k4. pb _tt[2] aa4. pb_d[28] b2. vss_io k5. vdd33 aa5. pb_bg2_ b3. vss_io k6. vdd33 aa6. pb_dvdd b4. pb_a[15] k21. vdd33 aa7. vdd33 b5. pb_a[20] k22. vdd33 aa8. vdd25 b6. pb_a[23] k23. pci_gnt[6]_ aa9. vdd25 b7. pb_a[25] k24. p1_trdy_ aa10. vdd33 b8. pb_a[29] k25. p1_frame_ aa11. vdd33
11. signals and pinout 216 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com b9. pb_dbg1_ k26. p1_ad[19] aa12. vss b10. pb_gbl_ l1. i2c_sclk aa13. vss b11. p1_ad[36] l2. pb_tbst_ aa14. vss b12. p1_ad[34] l3. pb_bg1_ aa15. vss b13. p1_ad[41] l4. pb_tt[4] aa16. vdd33 b14. p1_ad[44] l5. vdd33 aa17. vdd33 b15. p1_ad[49] l6. vdd33 aa18. vdd25 b16. p1_m66en l11. vss_io aa19. vdd25 b17. p1_ad[54] l12. vss_io aa20. vdd33 b18. p1_req[3]_ l13. vss_io aa21. p2_dvdd b19. p1_ad[59] l14. vss_io aa22. p2_inta_ b20. p1_ad[63] l15. vss_io aa23. p2_ad[13] b21. p1_cbe[6]_ l16. vss_io aa24. p2_ad[9] b22. p1_req64_ l21. vdd33 aa25. p2_cbe[0]_ b23. p1_64en_ l22. vdd33 aa26. p2_ad[7] b24. vss_io l23. p1_ad[14] ab1. pb_d[13] b25. vss_io l24. p1_perr_ ab2. pb_d[12] c1. pb_a[9] l25. p1_ad[16] ab3. int[3]_ c2. vss_io l26. p1_ad[22] ab4. pb_test1 c3. vss m1. pb_ap[1] ab5. vss_io c4. pb_a[13] m2. pb_ap[3] ab6. int[2]_ c5. pb_a[12] m3. pb_tsiz[1] ab7. pb_test2 c6. pb_dbg2_ m4. pb_tsiz[0] ab8. vdd25 c7. p1_rst_dir m5. pb _tsiz[2] ab9. vdd25 c8. pb_a[22] m6. vss ab10. vdd33 c9. pb_a[30] m11. vss_io ab11. vdd33 c10. pb_a[28] m12. vss_io ab12. pb_d[49] c11. pb_a[31] m13. vss_io ab13. vss c12. p1_ad[37] m14. vss_io ab14. vss c13. p1_ad[39] m15. vss_io ab15. p2_cbe[3]_ c14. p1_ad[47] m16. vss_io ab16. vdd33
11. signals and pinout 217 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com c15. p1_ad[50] m21. vss ab17. vdd33 c16. p1_ad[55] m22. p1_stop_ ab18. vdd25 c17. p1_req[4]_ m23. p1_ad[17] ab19. vdd25 c18. p1_ad[62] m24. p1_a d[18] ab20. p2_req[3]_ c19. p1_par64 m25. p1_ad[21] ab21. p2_test1 c20. p1_cbe[4]_ m26. p1_ad[23] ab22. vss_io c21. p1_cbe[5]_ n1. pb _dval_ ab23. p2_test2 c22. p1_clk n2. pb_t a_ ab24. p2_ad[14] c23. p1_avss n3. pb_ap[2] ab25. p2_ad[12] c24. p1_vdda n4. i2c_ sda ab26. p2_ad[10] c25. vss_io n5. vss ac1. pb_d[36] c26. p1_ad[4] n6 . vss ac2. vss_io d1. pb_a[6] n11. vss_io ac3. vss_io d2. pb_a[11] n12. vss_io ac4. vss_io d3. te n13. vss_io ac5. pb_dvss d4. vss n14. vss_io ac6. int[1]_ d5. jt_tdi n15. vss_io ac7. pb_d[3] d6. pb_a[17] n16. vss_io ac8. pb_d[11] d7. pb_a[14] n21. vss ac9. pb_d[42] d8. pb_a[16] n22. vss ac10. pb_d[10] d9. pb_a[18] n23. pci_req[5]_ ac11. po_rst_ d10. pb_a[26] n24. p 1_ad[20] ac12. pb_d[25] d11. pb_a[27] n25. p 1_cbe[3]_ ac13. pb_d[40] d12. p1_ad[38] n26. p 1_ad[24] ac14. pb_dp[5] d13. p1_ad[46] p1. pb _tea_ ac15. pb_dp[4] d14. p1_ad[48] p2. pb _d[15] ac16. p2_ad[26] d15. p1_ad[51] p3. pb _d[39] ac17. p2_ad[21] d16. p1_ad[57] p4. pb_ap[0] ac18. p2_irdy_ d17. p1_ad[60] p5. vss ac19. p2_devsel_ d18. enum_ p6. vss ac20. p2_trdy_ d19. p1_req[1]_ p11. vss_io ac21. p2_perr_
11. signals and pinout 218 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com d20. p1_gnt[1]_ p12. vss_io ac22. p2_dvss d21. p1_gnt[3]_ p13. vss_io ac23. vss_io d22. p1_dvss p14. vss_io ac24. vss_io d23. vss_io p15. vss_io ac25. vss_io d24. vss_io p16. vss_io ac26. p2_ad[11] d25. vss_io p21. vss ad1. pb_d[43] d26. p1_ad[8] p22. vss ad2. vss_io e1. pb_a[3] p23. p1_ad[28] ad3. pb_vdda e2. pb_rst_dir p24. pci_gnt[7]_ ad4. pb_avss e3. pb_a[10] p25. pci_req[6]_ ad5. pb_clk e4. es p26. p1_ad[25] ad6. pb_d[19] e5. vss r1. pb_d[30] ad7. pb_d[50] e6. vss r2. led_ ad8. pb_d[26] e7. jt_tck r3. pb_d[6] ad9. pb_d[57] e8. vdd25 r4. pb_d[47] ad10. int[0]_ e9. vdd25 r5. pb_d[37] ad11. pb_d[33] e10. vdd33 r6. vss ad12. pb_rst_ e11. vdd33 r11. vss_io ad13. pb_d[32] e12. pb_br1_ r12. vss_io ad14. p2_rst_dir e13. vss r13. vss_io ad15. pb_d[63] e14. vss r14. vss_io ad16. p2_ad[31] e15. p1_idsel r15. vss_io ad17. p2_ad[27] e16. vdd33 r16. vss_io ad18. p2_ad[20] e17. vdd33 r21. vss ad19. p2_cbe[2]_ e18. vdd25 r22. p2_ad[1] ad20. p2_ad[18] e19. vdd25 r23. p1_ad[29] ad21. p2_ad[19] e20. p1_test2 r24. p1_ad[31] ad22. p2_clk e21. p1_test1 r25. p 1_ad[27] ad23. p2_avss e22. vss_io r26. pci_gnt[5]_ ad24. p2_vdda e23. p1_ad[0] t1. pb_d[7] ad25. vss_io e24. p1_ad[2] t2. pb_d[22] ad26. p2_cbe[1]_
11. signals and pinout 219 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com e25. p1_ad[9] t3. pb_d[62] ae2. vss_io e26. p1_ad[7] t4. pb_d[21] ae3. vss_io f1. pb_a[0] t5. vdd33 ae4. pb_d[51] f2. pb_a[2] t6. vdd33 ae5. pb_d[4] f3. pb_dbg3_ t11. vss_io ae6. pb_d[58] f4. pb_a[7] t12. vss_io ae7. pb_d[18] f5. vss t13. vss_io ae8. pb_abb_ f6. vdd33 t14. vss_io ae9. pb_rstconf_ f7. vdd33 t15. vss_io ae10. pb_d[17] f8. vdd25 t16. vss_io ae11. pb_d[56] f9. vdd25 t21. vdd33 ae12. pb_fast f10. vdd33 t22. vdd33 ae13. pb_d[16] f11. vdd33 t23. p2_ad[0] ae14. pb_dp[6] f12. vss t24. p2_gnt [2]_ ae15. pb_dp[2] f13. vss t25. p1_ad[30] ae16. pb_dp[0] f14. vss t26. p1_ad[26] ae17. p2_ad[30] f15. vss u1. pb_d[55] ae18. p2_rst_ f16. vdd33 u2. pb_d[31] ae19. p2_ad[23] f17. vdd33 u3. pb_d[38] ae20. p2_ad[24] f18. vdd25 u4. pb_d[5] ae21. p2_ad[16] f19. vdd25 u5. vdd33 ae22. p2_serr_ f20. vdd33 u6. vdd33 ae23. p2_req[2]_ f21. p1_dvdd u21. vdd33 ae24. vss_io f22. p1_req[2]_ u22. vdd33 ae25. vss_io f23. p1_ad[1] u23. p2_ad[4] af3. pb_d[59] f24. p1_ad[5] u24. p2_ad[2] af4. pb_dbb_ f25. p1_ad[11] u25. p2_gnt[3]_ af5. pb_d[27] f26. p1_ad[10] u26. p1_rst_ af6. pb_d[34] g1. healthy_ v1. pb_d[23] af7. pb_d[2] g2. pb_tt[3] v2. pb_d[46] af8. pb_d[41] g3. pb_a[4] v3. pb_d[29] af9. pb_d[9]
11. signals and pinout 220 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com g4. pb_a[8] v4. pb_d [52] af10. pb_d[1] g5. vss v5. vdd25 af11. pb_d[48] g6. vdd33 v6. vdd25 af12. pb_d[24] g21. vdd33 v21. vdd25 af13. pb_d[8] g22. p1_ad[6] v22. vdd25 af14. pb_d[0] g23. p1_ad[3] v23. p2 _req[4]_ af15. pb_dp[7] g24. p1_ad[12] v24. p2 _ad[3] af16. pb_dp[3] g25. p1_par v25. p2_g nt[1]_ af17. pb_dp[1] g26. p1_cbe[1]_ v26. p2 _gnt[4]_ af18. p2_ad[29] h1. pb_aack_ w1. pb_d[54] af19. p2_ad[25] h2. pb_tt[0] w2. pb_d[14] af20. p2_ad[28] h3. pb_a[1] w3. pb_bg3_ af21. p2_ad[22] h4. pb_a[5] w4. pb_d[44] af22. p2_ad[17] h5. vdd25 w5. vdd25 af23. p2_frame_ h6. vdd25 w6. vdd25 af24. p2_stop_
11. signals and pinout 221 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 11.3 single pci powerspan ii pin information the powerspan ii single pci device is offered in two packages. the 484 pbga package is offered with a 23 mm body size and 1.00 mm ball pitch. the 420 hsbga package is offered with a 35 mm body size and 1.27 mm ball pitch. the 35 mm body size is the same as the original powerspan package offering. 11.3.1 single pci powerspan ii 420 hsbga figure 26 illustrates the top, side, and bott om views of the powerspan ii package. table 62: package characteristics feature description package type 420 hsbga package body size 35mm jedec specification jedec mo-151 variation bat-1
11. signals and pinout 222 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 26: 420 hsbga 11.3.1.1 package notes 1. all dimensions in mm 2. all dimensions and tolerance conform to ansi y14.5m - 1994 3. conforms to jedec ms-034 variation bar-1 notes: 1. all dimensions in mm. 2. all dimension and tolerances conform to ansi y14.5m-1994. 3. conforms to jedec mo-034 variation bar-1.
11. signals and pinout 223 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 11.3.2 420 hsbga pin information the following table shows the powerspan ii 420 hs bga pin information. this package is backwards compatible with the original powerspan?s 420 hpbga device. a1. vss_io g1. pb_tt[3] aa1. vss_io a2. vss_io g2. pb_a[1] aa2. pb_d[36] a3. jt_tdi g3. pb_a[5] aa3. pb_d[28] a4. jt_tdo g4. pb_a[3] aa4. pb_d[12] a5. jt_tck g5. vdd33 aa5. vdd33 a6. vss_io g22. vdd33 aa22. vdd33 a7. pb_a[30] g23. p1_ad[6] aa23. vss a8. p1_rst_dir g24. p1_ad[1] aa24. vss a9. vss_io g25. p1_ad[4] aa25. vss_io a10. pb_dbg1_ g26. p1_ad[3] aa26. vss_io a11. vss_io h1. pb_br3_ ab1. int[5]_ a12. p1_ad[34] h2. pb _tt[2] ab2. pb_d[44] a13. p1_ad[40] h3. pb _a[4] ab3. pb_d[43] a14. p1_ad[44] h4. pb _a[2] ab4. pb_d[35] a15. p1_ad[47] h5. vdd33 ab5. vss a16. vss_io h22. vdd33 ab6. vdd33 a17. p1_ad[50] h23. p1_ad[8] ab7. vdd33 a18. p1_ad[51] h24. p1_ad[9] ab8. vdd33 a19. p1_req[4]_ h25. pci_gnt[5]_ ab9. vss a20. p1_ad[59] h26. p1_test2 ab10. pb_dvdd a21. vss_io j1. healthy_ ab11. vdd25 a22. p1_vdda j2. vss_io ab12. vdd25 a23. p1_cbe[7]_ j3. pb_a[0] ab13. vss_io a24. p1_gnt[3]_ j4. int[4]_ ab14. vss_io a25. p1_clk j5. vss ab15. vdd25 a26. vss_io j22. vss ab16. vdd25 b1. te j23. p1_cbe[0]_ ab17. vdd25 b2. vss_io j24. p1_ad[7] ab18. vss
11. signals and pinout 224 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com b3. pb_a[13] j25. p 1_gnt[4]_ ab19. vdd33 b4. pb_a[19] j26. pci_gnt[6]_ ab20. vdd33 b5. pb_a[20] k1. pb_aack_ ab21. vdd33 b6. pb_a[18] k2. pb_tt[4] ab22. vss b7. pb_a[21] k3. pb_tt[0] ab23. pci_gnt[7]_ b8. pb_a[26] k4. pb_tt[1] ab24. vss_io b9. pb_dbg2_ k5. vdd25 ab25. vss_io b10. pb_br1_ k22. p1_dvdd ab26. nc b11. p1_ad[33] k23. p1_ad[12] ac1. jt_trst_ b12. p1_ad[32] k24. p1_ad[11] ac2. pb_d[53] b13. p1_ad[39] k25. p1_ad[10] ac3. pb_tea_ b14. p1_ad[41] k26. p1_ad[13] ac4. pb_avss b15. p1_ad[48] l1. vss_io ac5. nc b16. p1_ad[49] l2. pb_artry_ ac6. pb_d[3] b17. p1_ad[52] l3. pb_tsiz[3] ac7. led_ b18. p1_req[3]_ l4. pb_bg1_ ac8. vss b19. p1_ad[56] l5. vdd25 ac9. pb_d[19] b20. p1_idsel l22. vd d25 ac10. pb_d[27] b21. enum_ l23. p1_inta_ ac11. pb_d[18] b22. nc l24. p1_par ac12. pb_d[57] b23. p1_gnt[1]_ l25. p1_cbe[1]_ ac13. pb_d[41] b24. p1_64en_ l26. vs s_io ac14. pb_d[1] b25. vss_io m1. pb_ts_ ac15. pb_fast b26. vss_io m2. pb_tsiz[1] ac16. pb_d[24] c1. pb_rst_dir m3. pb _tbst_ ac17. pb_dp[6] c2. pb_a[10] m4. pb_t siz[2] ac18. pb_dp[3] c3. vss_io m5. vdd25 ac19. pb_d[63] c4. pb_a[17] m22. vdd25 ac20. pb_dp[5] c5. pb_a[15] m23. p1_ad[15] ac21. vss c6. pb_a[16] m24. p1_a d[14] ac22. pb_d[8] c7. pb_a[22] m25. p1_ad[5] ac23. vss
11. signals and pinout 225 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com c8. pb_a[25] m26. p 1_ad[2] ac24. vss_io c9. pb_a[29] n1. i2c_sclk ac25. p1_rst_ c10. pb_a[27] n2. pb_tsiz[0] ac26. p1_ad[31] c11. pb_gbl_ n3. pb_ap[3] ad1. int[3]_ c12. p1_ad[37] n4. pb _ap[2] ad2. pb_d[37] c13. vss_io n5. vss_io ad3. pb_dvss c14. nc n22. vss_io ad4. pb_d[31] c15. p1_serr_ n23. p1_frame_ ad5. pb_d[38] c16. p1_ad[53] n24. p 1_cbe[2]_ ad6. pb_d[14] c17. p1_ad[57] n25. p 1_perr_ ad7. pb_d[11] c18. p1_ad[60] n26. p1_stop_ ad8. pb_d[51] c19. p1_ad[61] p1. pb_ap[1] ad9. pb_d[42] c20. p1_cbe[6]_ p2 . nc ad10. pb_d[50] c21. p1_cbe[5]_ p3. pb_ta_ ad11. pb_d[34] c22. p1_req[1]_ p4. pb _ap[0] ad12. pb_d[2] c23. p1_ad[46] p5. vss_io ad13. pb_d[33] c24. vss_io p22. vss_io ad14. pb_d[9] c25. pb_ci_ p23. p1_ad[17] ad15. pb_d[48] c26. pci_req[5]_ p24. p1_ad[18] ad16. p2_test1 d1. pb_a[8] p25. p1_ad[19] ad17. pb_dp[7] d2. pb_a[11] p26. p1_irdy_ ad18. pb_dp[2] d3. pb_a[7] r1. vss_io ad19. pb_dp[4] d4. vss r2. pb_d[47] ad20. pb_dp[1] d5. pb_a[12] r3. pb_d [22] ad21. pb_d[0] d6. pb_a[14] r4. pb _d[7] ad22. vss d7. jt_tms r5. vdd25 ad23. vss_io d8. pb_a[23] r22. vdd25 ad24. vss_io d9. pb_a[24] r23. p1_test1 ad25. nc d10. pb_a[28] r24. p1_ad[21] ad26. vss_io d11. pb_a[31] r25. p1_ad[22] ae1. vss_io d12. p1_ad[35] r26. p1_ad[16] ae2. vss_io
11. signals and pinout 226 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com d13. p1_ad[43] t1. vss_io ae3. int[2]_ d14. p1_ad[45] t2. pb_d[6] ae4. pb_d[39] d15. p1_m66en t3. pb_d[55] ae5. pb_dbb_ d16. p1_ad[54] t4. pb_d[23] ae6. nc d17. p1_ad[58] t5. vdd25 ae7. pb_d[15] d18. p1_ad[63] t22. vdd25 ae8. pb_d[59] d19. p1_par64 t23. p1_ad[24] ae9. pb_vdda d20. p1_cbe[4]_ t24. p1_cbe[3]_ ae10. pb_d[58] d21. vss t25. p1_ad[20] ae11. pb_d[10] d22. p1_gnt[2]_ t26. vss_io ae12. vss_io d23. p1_avss u1. pb_d [30] ae13. pb_rstconf_ d24. p1_ad[42] u2. pb _d[54] ae14. pb_d[17] d25. p1_ad[36] u3. pb _d[46] ae15. pb_d[56] d26. p1_req[2]_ u4. pb _d[21] ae16. pb_d[40] e1. pb_dbg3_ u5. vdd25 ae17. nc e2. vss_io u22. vdd25 ae18. nc e3. pb_a[9] u23. nc ae19. vss_io e4. es u24. p1_ad[ 23] ae20. pb_dp[0] e5. vss u25. p1_ad[25] ae21. pb_d[32] e6. vdd33 u26. vss_io ae22. vss_io e7. vdd33 v1. pb_bg3_ ae23. vss_io e8. vdd33 v2. nc ae24. vss_io e9. vss v3. pb_d[29] ae25. vss_io e10. vdd25 v4. pb_d[5] ae26. nc e11. vdd25 v5. vss af1. vss_io e12. vdd25 v22. vss af2. pb_bg2_ e13. vss_io v23. p1_ad[27] af3. int[1]_ e14. vss_io v24. p1_ad[26] af4. pb_d[61] e15. vdd25 v25. vss_io af5. pb_clk e16. vdd25 v26. vss_io af6. vss_io e17. vdd25 w1. pb_d[62] af7. pb_dval_
11. signals and pinout 227 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 11.3.3 single pci powerspan ii 484 hsbga figure 27 illustrates the top, side, and bott om views of the powerspan ii package. e18. vss w2. pb_test2 af8. pb_abb_ e19. vdd33 w3. pb_d[45] af9. i2c_sda e20. vdd33 w4. pb_d[60] af10. pb_d[26] e21. vdd33 w5. vdd33 af11. vss_io e22. p1_dvss w22. vdd33 af12. pb_d[49] e23. p1_ad[62] w23. p1 _ad[30] af13. po_rst_ e24. p1_ad[38] w24. p1_ad[29] af14. pb_d[25] e25. p1_ad[55] w25. p1_ad[28] af15. pb_rst_ e26. pci_req[6]_ w26. pci_req[7]_ af16. vss_io f1. vss_io y1. pb_d[52] af17. pb_d[16] f2. pb_br2_ y2. pb_d [20] af18. int[0]_ f3. nc y3. pb_test1 af19. vss_io f4. pb_a[6] y4. pb_d [13] af20. pb_d[4] f5. vdd33 y5. vdd33 af21. vss_io f22. vdd33 y22. vdd33 af22. nc f23. p1_ack64_ y23. vss af23. nc f24. p1_ad[0] y24. p1_devsel_ af24. nc f25. p1_req64_ y25. p1_trdy_ af25. vss_io f26. vss_io y26. vss_io af26. vss_io table 63: package characteristics feature description package type 484 hsbga package body size 23mm jedec specification jedec ms-034 variation aaj-1
11. signals and pinout 228 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 27: 484 pbga 11.3.3.1 package notes 1. all dimensions in mm 2. all dimensions and tolerance conform to ansi y14.5m - 1994 3. conforms to jedec ms-034 variation aaj-1
11. signals and pinout 229 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 11.3.3.2 484 pbga pin information the following table shows the powerspan ii 484 pbga pin information. a1. pb_a[6] h9. vss_io r17. vdd33 a2. pb_a[13] h10. vss_io r18. vdd25 a3. te h11. vss_io r19. p1_ad[22] a4. jt_tms h12. vss_io r20. p1_ad[17] a5. pb_a[20] h13. vs s_io r21. p1_ad[5] a6. jt_tck h14. vss_io r22. p1_perr_ a7. pb_a[24] h15. vss_io t1. pb_test2 a8. pb_a[30] h16. vss t2. pb_d[21] a9. pb_a[27] h17. vdd33 t3. pb_d[52] a10. pb_dbg2_ h18. vdd25 t4. jt_trst_ a11. pb_gbl_ h19. pci_req[5]_ t5. vdd25 a12. p1_ad[34] h20. p1_ad[0] t6. vdd33 a13. p1_ad[32] h21. p1_req64_ t7. vss a14. p1_ad[40] h22. p1_ad[8] t8. vss a15. p1_ad[48] j1. pb_tsiz[2] t9. vss a16. p1_ad[53] j2. pb_tbst_ t10. vss a17. p1_ad[52] j3. pb_artry_ t11. vss a18. p1_ad[58] j4. pb_bg1_ t12. vss a19. p1_ad[60] j5. vdd25 t13. vss a20. p1_par64 j6. vdd33 t14. vss a21. enum_ j7. vss t15. vss a22. vss_io j8. vss_io t16. vss b1. pb_rst_dir j9. vss_io t17. vdd33 b2. es j10. vss_io t18. vdd25 b3. pb_a[14] j11. vss_io t19. p1_ad[25] b4. pb_a[12] j12. vs s_io t20. p1_ad[18] b5. jt_tdo j13. vss_io t21. p1_stop_ b6. pb_a[22] j14. vs s_io t22. p1_ad[19] b7. pb_a[21] j15. vss_io u1. pb_d[20]
11. signals and pinout 230 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com b8. pb_a[28] j16. vss u2. pb_d[45] b9. pb_a[31] j17. vdd33 u3. pb_d[36] b10. pb_br1_ j18. vdd25 u4. pb_d[43] b11. p1_ad[35] j19. pci_req[6]_ u5. vdd25 b12. p1_ad[37] j20. p1_cbe[0]_ u6. vdd33 b13. p1_ad[43] j21. p1_ad[4] u7. vdd33 b14. p1_ad[39] j22. p1_ad[9] u8. vdd33 b15. p1_ad[47] k1. pb_ap[2] u9. vdd33 b16. p1_ad[49] k2. pb _ap[3] u10. vdd33 b17. p1_ad[57] k3. pb_tsiz[0] u11. vdd33 b18. p1_ad[56] k4. pb _aack_ u12. vdd33 b19. p1_cbe[6]_ k5. vdd25 u13. vdd33 b20. p1_ad[59] k6. vdd33 u14. vdd33 b21. vss_io k7. vss u15. vdd33 b22. p1_vdda k8. vss_io u16. vdd33 c1. pb_a[11] k9. vss_io u17. vdd33 c2. pb_br2_ k10. vss_io u18. vdd25 c3. vss_io k11. vss_io u19. pci_req[7]_ c4. jt_tdi k12. vss_io u20. p1_ad[21] c5. pb_a[15] k13. vss_io u21. p1_ad[16] c6. pb_a[16] k14. vss_io u22. p1_irdy_ c7. pb_a[18] k15. vss_io v1. pb_d[5] c8. pb_a[25] k16. vss v2. int[5]_ c9. p1_rst_dir k17. vdd33 v3. pb_d[44] c10. pb_dbg1_ k18. vdd25 v4. pb_d[37] c11. p1_ad[33] k19. p1_ad[1] v5 . pb_tea_ c12. p1_ad[41] k20. p1_ad[7] v6. pb_d[35] c13. p1_ad[44] k21. p1_ad[12] v7. vdd25 c14. p1_serr_ k22. p1_ad[3] v8. vdd25 c15. p1_ad[50] l1. i2c_sclk v9. vdd25 c16. p1_ad[51] l2. pb_ap[1] v10. vdd25
11. signals and pinout 231 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com c17. p1_req[3]_ l3. pb_tsiz[1] v11. vdd25 c18. p1_ad[63] l4. pb_ts_ v12. vdd25 c19. p1_ad[61] l5. vdd25 v13. vdd25 c20. vss_io l6. vdd33 v14. vdd25 c21. p1_dvss l7. vss v15. vdd25 c22. p1_avss l8. vss_io v16. vdd25 d1. pb_a[2] l9. vss_io v17. vdd25 d2. pb_a[8] l10. vss_io v18. vdd25 d3. pb_dbg3_ l11. vss_io v19. p1_devsel_ d4. vss_io l12. vss_io v20. p1_cbe[3]_ d5. pb_a[10] l13. vss_io v21. p1_ad[20] d6. pb_a[17] l14. vs s_io v22. p1_test1 d7. pb_a[19] l15. vss_io w1. pb_d[60] d8. pb_a[23] l16. vss w2. pb_d[53] d9. pb_a[26] l17. vdd33 w3. pb_d[13] d10. pb_a[29] l18. vdd25 w4. vss_io d11. vdd25 l19. vdd25 w5. pb_bg2_ d12. p1_ad[45] l20. p1_test2 w6. int[1]_ d13. p1_m66en l21. p1_inta_ w7. int[2]_ d14. p1_ad[54] l22. pc i_gnt[5]_ w8. pb_d[61] d15. p1_req[4]_ m1. pb_d[47] w9. pb_d[42] d16. p1_idsel m2. pb_ta_ w10. pb_d[59] d17. p1_cbe[7]_ m3. pb_ap[0] w11. pb_d[18] d18. p1_cbe[5]_ m4. vdd25 w12. vdd25 d19. vss_io m5. vdd25 w13. pb_d[48] d20. p1_clk m6. vdd33 w14. pb_d[56] d21. p1_dvdd m7. vss w15. pb_dp[2] d22. pb_ci_ m8. vss_io w16. pb_d[63] e1. int[4]_ m9. vss_io w17. pb_d[8] e2. pb_a[1] m10. vss_io w18. pci_gnt[7]_ e3. pb_a[5] m11. vss_io w19. vdd25
11. signals and pinout 232 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com e4. pb_a[7] m12. vss_io w20. p1_ad[27] e5. vss_io m13. vss_io w21. p1_ad[26] e6. vdd25 m14. vss_io w22. p1_ad[24] e7. vdd25 m15. vss_io y1. pb_d[12] e8. vdd25 m16. vss y2. pb_d[28] e9. vdd25 m17. vdd33 y3. vss_io e10. vdd25 m18. vdd25 y4. pb_dvss e11. vdd25 m19. p1_ad[10] y5. pb_d[31] e12. vdd25 m20. p1_ad[13] y6. pb_d[3] e13. vdd25 m21. p1_ad[11] y7. pb_d[11] e14. vdd25 m22. p1_gnt[4]_ y8. pb_d[51] e15. vdd25 n1. pb_d[7] y9. pb_d[27] e16. vdd25 n2. pb_d[6] y10. pb_d[10] e17. vdd25 n3. pb_d[22] y11. pb_d[58] e18. p1_cbe[4]_ n4. pb_d[46] y12. pb_d[41] e19. p1_gnt[1]_ n5. vdd25 y13. pb_rstconf_ e20. p1_ad[46] n6. vdd33 y14. pb_d[1] e21. p1_ad[42] n7. vss y15. p2_test1 e22. p1_ack64_ n8. vss_io y16. pb_d[16] f1. pb_a[0] n9. vss_io y17. pb_dp[3] f2. pb_tt[2] n10. vss_io y18. pb_dp[0] f3. pb_a[4] n11. vss_io y19. pb_dp[1] f4. pb_a[9] n12. vss_io y20. p1_trdy_ f5. vdd25 n13. vss_io y21. p1_ad[23] f6. vss_io n14. vss_io y22. p1_ad[28] f7. vdd33 n15. vss_io aa1. int[3]_ f8. vdd33 n16. vss aa2. vss_io f9. vdd33 n17. vdd33 aa3. pb_avss f10. vdd33 n18. vdd25 aa4. pb_clk f11. vdd33 n19. p1_cbe[2]_ aa5. pb_d[38] f12. vdd33 n20. pci_gnt[6]_ aa6. pb_d[14]
11. signals and pinout 233 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com f13. vdd33 n21. p1_ad[15] aa7. pb_dval_ f14. vdd33 n22. p1_par aa8. pb_abb_ f15. vdd33 p1. pb_d[30] aa9. pb_d[50] f16. vdd33 p2. pb_d[55] aa10. pb_d[34] f17. vdd33 p3. pb_d[54] aa11. pb_d[2] f18. p1_req[1]_ p4. pb _d[23] aa12. pb_d[49] f19. p1_gnt[2]_ p5. vdd25 aa13. po_rst_ f20. p1_ad[62] p6. vdd33 aa14. pb_d[17] f21. p1_ad[36] p7. vss aa15. pb_rst_ f22. p1_ad[38] p8. vss_io aa16. pb_d[40] g1. pb_tt[1] p9. vss_io aa17. int[0]_ g2. pb_tt[0] p10. vss_io aa18. pb_dp[4] g3. pb_br3_ p11. vss_io aa19. pb_dp[5] g4. pb_a[3] p12. vss_io aa20. pb_d[32] g5. vdd25 p13. vss_io aa21. p1_ad[30] g6. vdd33 p14. vss_io aa22. p1_ad[29] g7. vss_io p15. vss_io ab1. vss_io g8. vss p16. vss ab2. pb_vdda g9. vss p17. vdd33 ab3. pb_dvdd g10. vss p18. vdd25 ab4. pb_d[39] g11. vss p19. p1_ad[2] ab5. pb_dbb_ g12. vss p20. p1_cbe[1]_ ab6. led_ g13. vss p21. p1_frame_ ab7. pb_d[15] g14. vss p22. p1_ad[14] ab8. pb_d[19] g15. vss r1. pb_d[62] ab9. i2c_sda g16. vss r2. pb_bg3_ ab10. pb_d[26] g17. vdd33 r3. pb_d[29] ab11. pb_d[57] g18. p1_gnt[3]_ r4. pb _test1 ab12. pb_d[33] g19. p1_64en_ r5. vdd25 ab13. pb_d[25] g20. p1_ad[6] r6. vdd33 ab14. pb_d[9] g21. p1_ad[55] r7. vss ab15. pb_fast
11. signals and pinout 234 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com g22. p1_req[2]_ r8. vss_io ab16. pb_d[24] h1. pb_tt[4] r9. vss_io ab17. pb_dp[7] h2. pb_tsiz[3] r10. vss_io ab18. pb_dp[6] h3. healthy_ r11. vss_io ab19. pb_d[4] h4. pb_tt[3] r12. vss_io ab20. pb_d[0] h5. vdd25 r13. vss_io ab21. p1_rst_ h6. vdd33 r14. vss_io ab22. p1_ad[31] h7. vss r15. vss_io h8. vss_io r16. vss
235 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12. register descriptions this chapter describes the registers used in powerspan ii. it describe s the register settings and bits which enable powerspan ii features and functi onality. the following topics are discussed: ? ?register access? on page 235 ? ?register reset? on page 245 ? ?configuration and iack cy cle generation? on page 246 ? ?register descriptions? on page 248 12.1 register access the powerspan ii registers can be accessed from bot h pci and the processor bu s. powerspan ii allows reads to its registers from all of its bus interfaces at the same time. however, writes may occur from only one bus interface at a time. 12.1.1 register map the 4 kbytes of powerspan ii control and status registers (pcsr) are us ed for pci control and status registers (csrs), and for overall powerspa n ii operation. the pcsr space is functionally divided into two areas: the pci csr space and the powerspan ii pcsr space. pscr space is accessible from the pr ocessor bus, pci-1 or pci-2 interfaces. table 64 is a detailed memory map for pcsr space a nd shows the powerspan ii register map for the dual pci powerspan ii. powerspan ii is available as both the single pci powerspan ii and dual pci powerspan ii. the shaded registers under pci-1 configuration and pci-2 configurat ion registers exist only if the associated pci interface is configur ed as the primary interface. a interface is configured as primary using a power-up option (see ?resets, clocks and power-up options? on page 167 for more information). the pci interface that is designated as primary has ad ded functionality which includes compactpci hot swap support, vital product data support and an i 2 c interface. refer to ?pci interface? on page 31 for more information on pr imary interface functionality. table 64: powerspan ii register map offset register mnemonic see pci-1 configuration registers 0x000 p1_id ?pci-1 id register? on page 250 0x004 p1_csr ?pci-1 control and status register.? on page 251
12. register descriptions 236 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 0x008 p1_class ?pci-1 class register? on page 254 0x00c p1_misc0 ?pci-1 miscellaneous 0 register? on page 255 0x010 p1_bsi2o ?pci-1 i2o target image base address register? on page 257 0x014 p1_bsreg ?pci-1 register image base address register? on page 258 0x018 p1_bst0 ?pci target base address register? on page 259 0x01c p1_bst1 ?pci target base address register? on page 259 0x020 p1_bst2 ?pci target base address register? on page 259 0x024 p1_bst3 ?pci target base address register? on page 259 0x028 pci unimplemented 0x02c p1_sid ?pci system id register? on page 260 0x030 pci unimplemented 0x034 p1_cap ?pci-1 capability pointer register? on page 261 0x038 pci unimplemented 0x03c p1_misc1 ?pci-1 miscellaneous 1 register? on page 262 0x040- 0x0e0 pci unimplemented 0x0e4 p1_hs_csr ?pci-1 compact pci hot swap control and status register? on page 264 0x0e8 p1_vpdc ?pci-1 vital product data capability register? on page 266 0x0ec p1_vpdd ?pci-1 vital product data register? on page 267 0x0f0-0x0fc pci unimplemented pci-1 registers 0x100 p1_ti0_ctl ?pci-1 target image x control register? on page 268 0x104 p1_ti0_taddr ?pci-1 target image x translation address register? on page 274 0x108-0x10c powerspan ii reserved 0x110 p1_ti1_ctl ?pci-1 target image x control register? on page 268 0x114 p1_ti1_taddr ?pci-1 target image x translation address register? on page 274 0x118-0x11c powerspan ii reserved 0x120 p1_ti2_ctl ?pci-1 target image x control register? on page 268 table 64: powerspan ii register map offset register mnemonic see
12. register descriptions 237 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 0x124 p1_ti2_taddr ?pci-1 target image x translation address register? on page 274 0x128-0x12c powerspan ii reserved 0x130 p1_ti3_ctl ?pci-1 target image x control register? on page 268 0x134 p1_ti3_taddr ?pci-1 target image x translation address register? on page 274 0x138-0x140 powerspan ii reserved 0x144 p1_conf_info ?pci-1 to pci-2 configuration cycle information register? on page 276 0x148 p1_conf_data ?pci-1 to pci-2 configuration cycle data register? on page 279 0x14c p1_iack ?pci-1 to pci-2 interrupt acknowledge cycle generation register? on page 280 0x150 p1_errcs ?pci-1 bus error control and status register? on page 281 0x154 p1_aerr ?pci-1 address error log register? on page 282 0x158-0x15c powerspan ii reserved 0x160 p1_misc_csr ?pci-1 miscellaneous control and status register? on page 283 0x164 p1_arb_ctrl ?pci-1 bus arbiter control register? on page 284 0x168-0x1fc powerspan ii reserved processor bu s registers 0x200 pb_si0_ctl ?processor bus slave image x control register? on page 287 0x204 pb_si0_taddr ?processor bus slave image x translation address register? on page 292 0x208 pb_si0_baddr ?processor bus slave image x base address register? on page 294 0x20c powerspan ii reserved 0x210 pb_si1_ctl ?processor bus slave image x control register? on page 287 0x214 pb_si1_taddr ?processor bus slave image x translation address register? on page 292 0x218 pb_si1_baddr ?processor bus slave image x base address register? on page 294 0x21c powerspan ii reserved 0x220 pb_si2_ctl ?processor bus slave image x control register? on page 287 0x224 pb_si2_taddr ?processor bus slave image x translation address register? on page 292 0x228 pb_si2_baddr ?processor bus slave image x base address register? on page 294 0x22c powerspan ii reserved table 64: powerspan ii register map offset register mnemonic see
12. register descriptions 238 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 0x230 pb_si3_ctl ?processor bus slave image x control register? on page 287 0x234 pb_si3_taddr ?processor bus slave image x translation address register? on page 292 0x238 pb_si3_baddr ?processor bus slave image x base address register? on page 294 0x23c powerspan ii reserved 0x240 pb_si4_ctl ?processor bus slave image x control register? on page 287 0x244 pb_si4_taddr ?processor bus slave image x translation address register? on page 292 0x248 pb_si4_baddr ?processor bus slave image x base address register? on page 294 0x24c powerspan ii reserved 0x250 pb_si5_ctl ?processor bus slave image x control register? on page 287 0x254 pb_si5_taddr ?processor bus slave image x translation address register? on page 292 0x258 pb_si5_baddr ?processor bus slave image x base address register? on page 294 0x25c powerspan ii reserved 0x260 pb_si6_ctl ?processor bus slave image x control register? on page 287 0x264 pb_si6_taddr ?processor bus slave image x translation address register? on page 292 0x268 pb_si6_baddr ?processor bus slave image x base address register? on page 294 0x26c powerspan ii reserved 0x270 pb_si7_ctl ?processor bus slave image x control register? on page 287 0x274 pb_si7_taddr ?processor bus slave image x translation address register? on page 292 0x278 pb_si7_baddr ?processor bus slave image x base address register? on page 294 0x27c powerspan ii reserved 0x280 pb_reg_baddr ?processor bus register image base address register? on page 295 0x284-0x28c powerspan ii reserved 0x290 pb_conf_info ?processor bus pci configuration cycle information register? on page 296 0x294 pb_conf_data ?processor bus configuration cycle data register? on page 299 0x298-0x29c powerspan ii reserved 0x2a0 pb_p1_iack ?processor bus to pci-1 interrupt acknowledge cycle generation register? on page 300 table 64: powerspan ii register map offset register mnemonic see
12. register descriptions 239 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 0x2a4 pb_p2_iack ?processor bus to pci-2 interrupt acknowledge cycle generation register? on page 301 0x2a8-0x2ac powerspan ii reserved 0x2b0 pb_errcs ?processor bus error control and status register? on page 302 0x2b4 pb_aerr ?processor bus address error log? on page 303 0x2b8-0x2bc powerspan ii reserved 0x2c0 pb_misc_csr ?processor bus miscellaneous control and status register? on page 304 0x2c4-0x2cc powerspan ii reserved 0x2d0 pb_arb_ctrl ?processor bus arbiter cont rol register? on page 307 0x2d4-0x2fc powerspan ii reserved dma registers 0x300 powerspan ii reserved 0x304 dma0_src_addr ?dma x source address register? on page 309 0x308 powerspan ii reserved 0x30c dma0_dst_addr ?dma x destination address register? on page 310 0x310 powerspan ii reserved 0x314 dma0_tcr ?dma x transfer control register? on page 311 0x318 powerspan ii reserved 0x31c dma0_cpp ?dma x command packet pointer register? on page 313 0x320 dma0_gcsr ?dma x general control and status register? on page 314 0x324 dma0_attr ?dma x attributes register? on page 317 0x328-0x330 powerspan ii reserved 0x334 dma1_src_addr ?dma x source address register? on page 309 0x338 powerspan ii reserved 0x33c dma1_dst_addr ?dma x destination address register? on page 310 0x340 powerspan ii reserved 0x344 dma1_tcr ?dma x transfer control register? on page 311 0x348 powerspan ii reserved table 64: powerspan ii register map offset register mnemonic see
12. register descriptions 240 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 0x34c dma1_cpp ?dma x command packet pointer register? on page 313 0x350 dma1_gcsr ?dma x general control and status register? on page 314 0x354 dma1_attr ?dma x attributes register? on page 317 0x358-0x360 powerspan ii reserved 0x364 dma2_src_addr ?dma x source address register? on page 309 0x368 powerspan ii reserved 0x36c dma2_dst_addr ?dma x destination address register? on page 310 0x370 powerspan ii reserved 0x374 dma2_tcr ?dma x transfer control register? on page 311 0x378 powerspan ii reserved 0x37c dma2_cpp ?dma x command packet pointer register? on page 313 0x380 dma2_gcsr ?dma x general control and status register? on page 314 0x384 dma2_attr ?dma x attributes register? on page 317 0x388-0x390 powerspan ii reserved 0x394 dma3_src_addr ?dma x source address register? on page 309 0x398 powerspan ii reserved 0x39c dma3_dst_addr ?dma x destination address register? on page 310 0x3a0 powerspan ii reserved 0x3a4 dma3_tcr ?dma x transfer control register? on page 311 0x3a8 powerspan ii reserved 0x3ac dma3_cpp ?dma x command packet pointer register? on page 313 0x3b0 dma3_gcsr ?dma x general control and status register? on page 314 0x3b4 dma3_attr ?dma x attributes register? on page 317 0x3b8-0x3fc powerspan ii reserved miscellaneous registers 0x400 misc_csr ?miscellaneous control and status register? on page 318 0x404 clock_ctl ?clock control register? on page 321 table 64: powerspan ii register map offset register mnemonic see
12. register descriptions 241 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 0x408 i2c_csr ?i2c/eeprom interface control and status register? on page 322 0x40c rst_csr ?reset control and status register? on page 324 0x410 isr0 ?interrupt status register 0? on page 327 0x414 isr1 ?interrupt status register 1? on page 329 0x418 ier0 ?interrupt enable register 0? on page 332 0x41c ier1 ?interrupt enable register 1? on page 334 0x420 imr_mbox ?interrupt map register mail box? on page 337 0x424 imr_db ?interrupt map register doorbell? on page 339 0x428 imr_dma ?interrupt map register dma? on page 340 0x42c imr_hw ?interrupt map register hardware? on page 341 0x430 imr_p1 ?interrupt map register pci-1? on page 342 0x434 imr_p2 ?interrupt map register pci-2? on page 343 0x438 imr_pb ?interrupt map register processor bus? on page 344 0x43c imr2_pb ?interrupt map register two processor bus? on page 345 0x440 imr_misc ?interrupt map register miscellaneous? on page 346 0x444 idr ?interrupt direction register? on page 347 0x448-0x44c powerspan ii reserved 0x450 mbox0 ?mailbox x register? on page 349 0x454 mbox1 ?mailbox x register? on page 349 0x458 mbox2 ?mailbox x register? on page 349 0x45c mbox3 ?mailbox x register? on page 349 0x460 mbox4 ?mailbox x register? on page 349 0x464 mbox5 ?mailbox x register? on page 349 0x468 mbox6 ?mailbox x register? on page 349 0x46c mbox7 ?mailbox x register? on page 349 0x470 sema0 ?semaphore 0 register? on page 350 0x474 sema1 ?semaphore 1 register? on page 351 table 64: powerspan ii register map offset register mnemonic see
12. register descriptions 242 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 0x478-0x4fc powerspan ii reserved i 2 o registers 0x500 pci_ti2o_ctl ?pci i2o target image control register? on page 352 0x504 pci_ti2o_taddr ?pci i2o target image translation address register? on page 356 0x508 i2o_csr ?i2o control and status register? on page 357 0x50c i2o_queue_bs ?i2o queue base address register? on page 360 0x510 ifl_bot ?i2o inbound free list bottom pointer register? on page 362 0x514 ifl_top ?i2o inbound free list top pointer register? on page 363 0x518 ifl_top_inc ?inbound free list top pointer increment register? on page 364 0x51c ipl_bot ?i2o inbound post list bottom pointer register? on page 365 0x520 ipl_bot_inc ?i2o inbound post list bottom pointer increment register? on page 366 0x524 ipl_top ?i2o inbound post list top pointer register? on page 367 0x528 ofl_bot ?i2o outbound free list bottom pointer register? on page 368 0x52c ofl_bot_inc ?i2o outbound free list bottom pointer increment register? on page 369 0x530 ofl_top ?i2o outbound free list top pointer register? on page 370 0x534 opl_bot ?i2o outbound post list bottom pointer register? on page 371 0x538 opl_top ?i2o outbound post list top pointer register? on page 372 0x53c opl_top_inc ?i2o outbound post list top pointer increment register? on page 373 0x540 host_oio ?i2o host outbound index offset register? on page 374 0x544 host_oia ?i2o host outbound index alias register? on page 375 0x548 iop_oi ?i2o iop outbound index register? on page 376 0x54c iop_oi_inc ?i2o iop outbound index increment register? on page 377 0x550-0x7fc powerspan ii reserved pci-2 configuration registers (dual pci powerspan ii) the pci-2 configuration registers are func tionally identical to the pci-1 configur ation registers from offsets 0x000-0fc. documentation of the pci-2 configuration space is the same as the pci-1 interface, shifting the register offsets up by 0x800 an d swapping pci-1 and pci-2 everywhere. 0x800 p2_id pci-2 id register table 64: powerspan ii register map offset register mnemonic see
12. register descriptions 243 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 0x804 p2_csr pci-2 control and status register 0x808 p2_class pci-2 class register 0x80c p2_misc0 pci-2 miscellaneous 0 register 0x810 p2_bsi2o pci-2 i 2 o target image base address register 0x814 p2_bsreg pci-2 register image base address register 0x818 p2_bst0 pci-2 target image 0 base address register 0x81c p2_bst1 pci-2 target image 1 base address register 0x820 p2_bst2 pci-2 target image 2 base address register 0x824 p2_bst3 pci-2 target image 3 base address register 0x828 pci unimplemented 0x82c p2_sid pci-2 subsystem id register 0x830 pci unimplemented 0x834 p2_cap pci-2 capability pointer register 0x838 pci unimplemented 0x83c p2_misc1 pci-2 miscellaneous 1 register 0x840-0x8e0 pci unimplemented 0x8e4 p2_hs_csr pci-2 compact pci hot swap control and status register 0x8e8 p2_vpdc pci-2 vital product data capability register 0x8ec p2_vpdd pci-2 vital product data register 0x8f0-0x8fc pci unimplemented pci-2 registers (dual pci powerspan ii) the pci-2 target image control and status registers are functi onally identical to the pci-1 target image control and status registers from offsets 0x100-1fc. documentation of the pci-2 target images is the same as the pci-1 images, shifting the register offsets up by 0x800 and swap ping pci-1 and pci-2 everywhere. 0x900 p2_ti0_ctl pci-2 target image 0 control register 0x904 p2_ti0_taddr pci-2 target image 0 translation address register 0x908-0x90c powerspan ii reserved 0x910 p2_ti1_ctl pci-2 target image 1 control register 0x914 p2_ti1_taddr pci-2 target image 1 translation address register table 64: powerspan ii register map offset register mnemonic see
12. register descriptions 244 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.1.2 access from pci the pci-1 register image base address register sp ecifies the 4-kbyte aligne d base address for the powerspan ii control and status registers (pcsrs) in pci memory space. the base address for pcsr space is enabled by: 1. setting the bsreg_bar_en bit in the p1_misc_cs 2. writing to the p1_bsreg register either with a pci configuration write access or by writing to it from the processor bus (pb). once enabled, the pcsr space can be accessed in pci memory space with si ngle-beat 32-bit accesses. 0x918-0x91c powerspan ii reserved 0x920 p2_ti2_ctl pci-2 target image 2 control register 0x924 p2_ti2_taddr pci-2 target image 2 translation address register 0x928-0x92c powerspan ii reserved 0x930 p2_ti3_ctl pci-2 target image 3 control register 0x934 p2_ti3_taddr pci-2 target image 3 translation address register 0x938-0x940 powerspan ii reserved 0x944 p2_conf_info pci-2 to pci 1 conf iguration cycle information register 0x948 p2_conf_data pci-2 to pci 1 configuration cycle data register 0x94c p2_iack pci-2 to pci 1 interrupt acknowledge cycle generation register 0x950 p2_errcs pci-2 bus error control and st atus register 0x954 p2_aerr pci-2 address error log register 0x958-0x95c powerspan ii reserved 0x960 p2_misc_csr pci-2 miscellaneous control and status register 0x964 p2_arb_ctrl pci-2 bus arbiter control register 0x968-0xffc powerspan ii reserved table 64: powerspan ii register map offset register mnemonic see
12. register descriptions 245 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.1.3 access from the processor bus the pb_reg_baddr register specif ies the 4-kbyte aligned base a ddress for pcsr space on the processor bus. this register is programmed th rough any register interface or through eeprom. register accesses through the proces sor bus interface can be big-endian or powerpc little-endian (see ?processor bus and powerspan ii register transfers? on page 179 ). the endian conversion for register accesses from the processor bus interface is controlled with the end bit in the pb_reg_baddr register. the default mode is big-endian. the reset state for the base address for pcsr space on the processor bus is 0x3000_0000. 12.1.4 access from multiple interfaces powerspan ii allows reads to its re gisters from all of its bus interf aces at the same time. however, writes may occur from only one bus interface at a time . this prevents data corruption if two or more interfaces try to write to the same register simultaneously. powerspan ii uses an internal round robin arbitrat ion mechanism for register access from the different bus interfaces. register writes are retried until the interface doing the write has successfu lly arbitrated for register access. each powerspan ii pci target has a px lockout (px_loc kout) bit in the ?miscellaneous control and status register? on page 318 (misc_csr). while a lockout bit is set, the corresponding pci target retries all configuration type 0 transactio ns. when the base address registers have been configured, memory transactions are claimed, but th ey are retried until the lo ckout bit is cleared. by default the px_lockout bits are set. the lockout bi ts can either be cleared by eeprom load, or by an access from the processor bus interface. the lockout bits are automatically cleared by powerspan ii when the pwrup_boot bit in the ?processor bus arbiter control register? on page 307 is set to pci. 12.2 register reset the pcsr space is divided into four reset domains: ? pci-1 csr space ? pci-2 csr space ? processor bus interface registers ? device specific registers see ?reset response? on page 168 for a detailed description of register reset partitioning. register writes to ?write 1 to set/clear? status bits may not be reflected by an immediate register read. register accesses from all interfaces are retried during eeprom load.
12. register descriptions 246 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com when an eeprom is detected by powerspan ii?s i 2 c interface after reset, certain registers are initialized with the contents of the eeprom. see ?i2c/eeprom? on page 127 for details on which register fields are loaded through eeprom. 12.3 configuration and iack cycle generation powerspan ii has registers that must be program med in order for a pci master to generate configuration (type 1 or 0) and iack transactions on the alternate pci interface and for the processor bus to generate configuration (type 1 or 0) and iack transactions on either pci bus. 12.3.1 from pci-to-pci the following powerspan ii registers are used by a pci master to gene rate configuration (type 1 or 0) and iack transactions on th e alternate pci interface: ? px_conf_info/px_conf_data ?px_iack 12.3.1.1 pci configuration data generating a configuration tr ansaction on pci requires the programming of the ?pci-1 to pci-2 configuration cycle inform ation register? on page 276 (px_conf_info) in order set-up the address of the configuration cycle. the pci transaction is generated when a register access occurs on the ?pci-1 to pci-2 configuration cycle data register? on page 279 (px_conf_data). when a register write is performed to px_con f_data, the address and data parameters in px_conf_data are used to generate a confi guration transaction on the alternate pci bus. when a register read is performed to px_conf_data , the read is retried wh ile a configuration read transaction is generated on the al ternate pci bus. the address for th e read transaction is defined by px_conf_info. while the data is being retrieved, register accesses to px_conf_data is retried. the px_conf_info and px_conf_data registers must be treated as shared resources for applications that require more than one agent to generate conf iguration transactions on pci. a semaphore is used to control access. 12.3.1.2 interrupt acknowledge generation the px_iack register is used to generate iack read s on the alternate pci bus. if a register read is performed to px_iack, then the read is retried wh ile an iack cycle is generated on the alternate pci bus. the address for the iack cycle is ta ken directly from the originating pci bus. the px_iack register must be treated as shared reso urces for applications that require more than one agent to generate iack transactions on pc i. a semaphore is used to control access. writes to px_iack have no effect.
12. register descriptions 247 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.3.2 from the processor bus to pci the following powerspan ii registers are used to generate configuration (type 1 or 0) and iack transactions going from the processor bus interface to either of the pci interfaces: ? pb_conf_info/pb_conf_data ? pb_px_iack 12.3.2.1 processor bus configuration data generating a configuration tr ansaction on pci requires the programming of the ?pci-1 to pci-2 configuration cycle information register? on page 276 (pb_conf_info) to set-up the address of the configuration cycle. the dest bit selects the pci bus for the configuration access. the pci transaction is generated when the user performs a register access to the ?pci-1 to pci-2 configuration cycle data register? on page 279 (pb_conf_data). when a register write is perfo rmed to pb_conf_data, the addr ess and data parameters in pb_conf_data are used to generate a configur ation transaction on the selected pci bus. the processor bus slave response to the read of pb_conf_data is dependent on the state the address retry enable (artry_en) bit of the ?processor bus miscellane ous control and status register? on page 304 . if artry_en is disabled, the proce ssor bus slave clai ms the read of pb_conf_data. the processor bus slave only assert s pb_ta_ to complete the transaction when the read data is returned from pci. if artry_en is enabled, the read of pb_conf_data is retried immediately. subsequent register accesses to pb_conf_data wi ll be retried until the data is returned from pci. 12.3.2.2 interrupt acknowledge generation the pb_px_iack registers are used to generate iack reads on the pci interfaces.the address for the iack cycle is taken direc tly from the processor bus. the processor bus slave response to the read of pb _px_iack is dependent on the state of the address retry enable (artry_en) bit of the ?processor bus miscellaneous cont rol and status register? on page 304 . if artry_en is disabled, the processor bus slave claims the read of pb_px_iack. the processor bus slave only asserts pb _ta_ to complete the transaction when the read data is returned from pci. if artry_en is enabled, the read of pb_px_iack is retried immediately. subsequent register accesses to pb_px_iack are retrie d until the data is returned from pci. applications that require more than one agent to generate iack transact ions on pci must use a semaphore to control pb_p1_iack and pb_p2_iack. writes to pb_px_iack have no effect.
12. register descriptions 248 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.4 bit ordering and endian ordering the register tables in ?register descriptions? on page 248 provide bit ordering in both pci little-endian and powerpc big-endi an. the register table from the ?pci-1 control and status register.? on page 251 is repeated here. the ?pci bits? in the left hand column give the addressing of the register bits when the register is accessed from the pci bus in little-endian mode. the ?pb bits? in the far right hand column give the addressing of the register bi ts when the register is accessed from the processor bus in big-endian mode. please consult ?endian mapping? on page 177 for a full endian discussion. 12.5 register descriptions in the following detailed descriptions of each register, the shaded regist er bits are different for the dual pci powerspan ii and single pci powerspan ii table 65 describes the abbreviations used in the register descriptions. pci bits function pb bits 31-24 d_pe s_ serr r_ma r_ta s_ta devsel mdp_d 0-7 23-16 tfbbc 0 dev66 cap_l pci reserved 8-15 15-08 pci reserved mfbbc serr_en 16-23 07-00 wait peresp vgaps mwi_ en sc bm ms ios 24-31 throughout the manual, register fields are given assuming pc i little-endian bit ordering. the user must consult the regi ster table to obtain the corresponding powerpc big-endian bit ordering. table 65: abbreviations used in register descriptions abbreviation description g_rst general reset (active when either pb _rst, p1_rst, or p 2_rst is asserted) pb_rst processor bus reset p1_rst pci-1 (p1) reset p2_rst pci-2 (p2) reset px_rst pci-1 or pci-2 reset
12. register descriptions 249 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com pri_rst primary pci reset r/w read/write r read only r/write 1 to clear read/write 1 to clear write 1 to set read 0/write 1 to set (writing a 1 triggers an event) r/wpb read only from pci, read/write from processor bus 0 eeprom reset value is 0. register bit may be loaded by eeprom after reset 1 eeprom reset value is 1. register bit may be loaded by eeprom after reset pwrup register bit loaded as a power-up option pci reserved do not write. read back 0 pci unimplemented do not write. read back 0 powerspan ii reserved do not write. read back undefined reserved do not write. read back undefined single pci powerspan ii single pci powerspan ii (pci-1 and processor bus) table 65: abbreviations used in register descriptions abbreviation description
12. register descriptions 250 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.1 pci-1 id register this register is read only from pci-1 and read/write from the processor bus interface. register name: p1_id register offset: 0x000 pci bits function pb bits 31-24 did 0-7 23-16 did 8-15 15-08 vid 16-23 07-00 vid 24-31 name type reset by reset state function did[15:0] r/write from processor bus p1_rst 0x8260 eeprom device id idt allocated device identifier did[15:0] r/write from processor bus p1_rst 0x8261 single pci powerspan ii vid[15:0] r/write from processor bus p1_rst 0x10e3 eeprom vendor id pci sig allocated vendor identifier note: idt acquired tundra semiconductor.
12. register descriptions 251 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.2 pci-1 control and status register. register name: p1_csr register offset: 0x004 pci bits function pb bits 31-24 d_pe s_ serr r_ma r_ta s_ta devsel mdp_d 0-7 23-16 tfbbc 0 dev66 cap_l pci reserved 8-15 15-08 pci reserved mfbbc serr_en 16-23 07-00 wait peresp vgaps mwi_ en sc bm ms ios 24-31 name type reset by reset state function d_pe r/w 1 to clear p1_rst 0 detected parity error this bit is set by the device whenever the master module detects a data parity error or the target module detects a data or address parity error. 0 = no parity error 1 = parity error s_serr r/w 1 to clear p1_rst 0 signaled serr# the device as pci target sets this bit when it asserts serr# to signal an address parity error. serr_en and peresp must be set before serr# can be asserted. 0 = serr# not asserted 1 = serr# asserted r_ma r/w 1 to clear p1_rst 0 received master abort the device sets this bit when a transaction it initiated had to be terminated with a master-abort. 0 = device did not generate master-abort 1 = device generated master abort r_ta r/w 1 to clear p1_rst 0 received target abort the device sets this bit when a transaction it initiated was terminated with a target-abort. 0 = device did not detect target-abort 1 = device detected target-abort
12. register descriptions 252 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com s_ta r/w 1 to clear p1_rst 0 signaled target-abort 0 = device target module did not terminate transaction with target-abort 1 = device target module terminated transaction with target-abort. devsel [1:0] r p1_rst 01 device select timing the device is a medium speed device. mdp_d r/w 1 to clear p1_rst 0 master data parity detected the device sets this bit if the peresp bit is set and either (a) it is the master of the transaction in which it asserts perr#, or (b) the addressed target asserts perr#. 0 = master module did not detect/generate data parity error 1 = master module detected/generated data parity error tfbbc r p1_rst 0 target fast back to back capable warning: powerspan ii cannot accept fast back-to-back transactions - neither as the same agent nor as a different agent. dev66 r p1_rst 1 device 66 mhz the device is a 66 mhz capable device cap_l r p1_rst pwrup capabilities list the capabilities list is only supported by the primary pci interface. when pci-1 is the primary interface, cap_l in pci-1 is set and cap_l in pci-2 is cleared. the opposite is true when pci-2 is the primar y interface. the primary pci interface is determined by the pwrup_pri_pci power-up option. 0 = capabilities list unsupported 1 = capabilities list supported mfbbc r p1_rst 0 master fast back to back enable the device does not generate fast back to back transactions serr_en r/w p1_rst 0 serr# enable setting this and peresp allows the device to report address parity errors with serr# as pci target. 0 = disable serr# driver 1 = enable serr# driver wait r p1_rst 0 wait cycle control 0 = no address/data stepping name type reset by reset state function
12. register descriptions 253 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com peresp r/w p1_rst 0 parity error response controls the device?s response to address and data parity errors. when enabled, perr# is asserted and the mdp_d bit is set in response to data parity errors. when this bit and serr_en are set, the device reports address parity errors on serr#. this bit does not affect the device?s parity generation. 0 = disable 1 = enable vgaps r p1_rst 0 vga palette snoop 0 = disable mwi_en r p1_rst 0 memory write and invalidate enable powerspan ii does not generate mwi transactions. 0 = disable sc r p1_rst 0 special cycles powerspan ii does not respond to special cycles as a pci target. 0 = disable bm r/w p1_rst 0 eeprom bus master enables the device to generate cycles as a pci master. 0 = disable 1 = enable ms r/w p1_rst 0 eeprom enables the device to accept memory cycles as a pci target. memory space 0 = disable 1 = enable ios r p1_rst 0 io space powerspan ii does not respond to i/o cycles as a pci target. 0 = disable name type reset by reset state function
12. register descriptions 254 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.3 pci-1 class register register name: p1_class register offset: 0x008 pci bits function pb bits 31-24 base 0-7 23-16 sub 8-15 15-08 prog 16-23 07-00 rid 24-31 name type reset by reset state function base[7:0] r/wpb p1_rst 0x06 eeprom base class code when powerspan ii is an i 2 o controller, this field must be programmed with 0x0e either fr om the processor bus or by eeprom. 0x06 = bridge device (default) 0x0e = i2o controller sub[7:0] r/wpb p1_rst 0x80 eeprom sub class code when powerspan ii is an i 2 o controller, this field must be programmed with 0x00 either from the processor bus or by eeprom. 0x80 = other bridge device (if base = 0x06) 0x00 = i2o device (if base = 0x0e) prog[7:0] r/wpb p1_rst 0x00 eeprom programming interface when powerspan ii is an i 2 o controller, this field must be programmed with 0x01 either from the processor bus or by eeprom. 0x00 = other bridge device (if base = 06) 0x01 = i2o inbound and outbound queues mapped to offsets 0x40 and 0x44 respectively, and i2o interrupt status and mask registers at offsets 0x30 and 0x34 (if base = 0x0e) rid[7:0] r/wpb p1_rst 0x01 eeprom revision id 0x01 = powerspan ii
12. register descriptions 255 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.4 pci-1 miscellaneous 0 register register name: p1_misc0 register offset: 0x00c pci bits function pb bits 31-24 bistc sbist pci reserved ccode 0-7 23-16 mfunct layout 8-15 15-08 ltimer 16-23 07-00 cline 24-31 name type reset by reset state function bist r p1_rst 0 bist capable 0 = device is not bist capable sbist r p1_rst 0 start bist 0 = device is not bist capable ccode [3:0] r p1_rst 0 completion code 0 = device is not bist capable mfunct r p1_rst 0 multifunction device 0 = device is not a multifunction device layout [6:0] r p1_rst 0 configuration space layout ltimer [7:0] r/w p1_rst 0 latency timer number of pci bus clocks before the device must initiate termination of transaction as a master. resolution of one clock. this field specifies the value of the latency timer for the pci-1 master in units of pci bus clocks. the latency timer provides a resolution of one pci bus clock. this timer always has a minimum value of eight pci bus clocks. the values 000b-111b correspond to eight clock cycles.
12. register descriptions 256 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com cline[7:0] the cline size specifies the system cacheline size in units of 32-bit words. the cline is used by the powerspan ii pci master in dete rmining which pci read cy cle it generates on pci (mr, mrl, mrm). table 66 shows the relationship between the read amount and the read command. cline[7:0] r/w p1_rst 0 cacheline size specifies the cacheline size for this interface, in number of 32-bit words. valid settings are 4, 8, 16 or 32 words. default setting is 8 words. all other settings default to 8 words. 0x00 = 8 x 32-bit words 0x04 = 4 x 32 bit words 0x08 = 8 x 32-bit words 0x10 = 16 x 32-bit words 0x20 = 32 x 32 bit words others = 8 x 32-bit words table 66: read amount versus read command read amount read command < 8 bytes memory read <= cline memory read line > cline memory read multiple name type reset by reset state function
12. register descriptions 257 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.5 pci-1 i2o target im age base address register this register specifies the 64 kbyte alig ned base address of the device?s pci i 2 o target image in pci memory space. powerspan ii only supports the i 2 o target image on the primary pci interface. the first 4 kbytes of this image provides the i 2 o shell interface inbound and outbound queues and the host interrupt status and mask registers. cycles claimed by the powerspan ii i 2 o target image with offsets greater than 4 kbytes is passed on to th e processor bus. the cont rol information for the powerspan ii i 2 o target image is fully defined in the pci_ti2o_ctl and pci_ti2o_taddr registers. a write must occur to this register before the device?s i 2 o target image is accessed through pci memory transactions. this write can be performed with either a pci configuration transa ction or a register access by the local processor. a base address of 0x00000 is not a supported base ad dress and the register image does not respond to pci transactions as a target device when 0x00000 is written to this field ? the image is disabled. powerspan ii supports a base address of 0x00000 if the bar_eq_0 bit is set in the ?miscellaneous control and status register? on page 318 . the bs field in the ?pci i2o target image control register? on page 352 determines the size of the image requested in pci me mory space for the pci i 2 o target image. writes are enabled to this regist er only if the bar_en bit in the pci_ti2o_ctl register is set. this register is not implemente d in the secondary pci interface. register name: p1_bsi2o register offset: 0x010 pci bits function pb bits 31-24 ba 0-7 23-16 ba 8-15 15-08 0 0 0 0 0 0 0 0 16-23 07-00 0 0 0 0 prftch type space 24-31 name type reset by reset state function ba[15:0] r/w p1_rst 0 base address prftch r/wpb p1_rst 1 eeprom prefetchable memory is prefetchable type [1:0] r p1_rst 0 type 00 = locate anywhere in 32-bit address space space r p1_rst 0 pci bus address space 0 = memory
12. register descriptions 258 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.6 pci-1 register image base address register this register specifies the 4-kbyt e aligned base address of the devi ce?s register space in pci memory space. the register space is only 4 kbyte, therefore th e pci address lines [11:0] are used to select the register. a write must occur to this regist er before the device?s registers can be accessed through pci memory transactions. this write can be pe rformed with a pci configuration tr ansaction or a re gister access by the local processor. a base address of 0x00000 is not a supported base ad dress and the register image does not respond to pci transactions as a target device wh en 0x00000 is written to this field ? the image is disabled. powerspan ii supports a base address of 0x00000 if the bar_eq_0 bit is set in the ?miscellaneous control and status register? on page 318 . writes are enabled to this register only when the bsreg_bar_en bit in the ?pci-1 miscellaneous control and status register? on page 283 is set. register name: p1_bsreg register offset: 0x014 pci bits function pb bits 31-24 ba 0-7 23-16 ba 8-15 15-08 ba 0 0 0 0 16-23 07-00 0 0 0 0 prftch type space 24-31 name type reset by reset state function ba[19:0] r/w p1_rst 0 base address prftch r p1_rst 0 prefetchable memory is not prefetchable type [1:0] r p1_rst 0 type 00 = locate anywhere in 32-bit address space space r p1_rst 0 pci bus address space 0 = memory
12. register descriptions 259 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.7 pci target base address register this register specifies the 64-kbyte aligned ba se address of the device?s pci target image x in pci memory space. a write must occur to this register before the device?s pci target image x is accessed through pci memory transactions. this write is performed with a pci configuration transact ion or a register access by the local processor. a base address of 0x00000 is not a supported base address and the regi ster image does not respond to pci transactions as a target device when 0x00000 is written to this field ? the image is disabled. powerspan ii supports a base address of 0x00000 if the bar_eq_0 bit is set in the ?miscellaneous control and status register? on page 318 . the bs field of the ?pci-1 target image x control register? on page 268 determines the size of the image requested in pci memory space for pci target image x. writes are enabled to th is register only when the bar_en bit in the p1_tix_ctl register is set. reads from this image are treated as prefetchable. the prftch field is programmable to provide flexibility for the bios. register name: p1_bstx register offset: 0x018, 0x01c, 0x020, 0x024 pci bits function pb bits 31-24 ba 0-7 23-16 ba 8-15 15-08 0 0 0 0 0 0 0 0 16-23 07-00 0 0 0 0 prftch type space 24-31 name type reset by reset state function ba[15:0] r/w p1_rst 0 base address prftch r/wpb p1_rst 1 eeprom prefetchable memory is prefetchable type [1:0] r p1_rst 0 type 00 = locate anywhere in 32-bit address space space r p1_rst 0 pci bus address space 0 = memory space
12. register descriptions 260 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.8 pci system id register writes to the pci_sid register fro m the processor propagates to its contents. writes to the p1_sid register from the pci bus have no effect on its contents. register name: p1_sid register offset: 0x02c pci bits function pb bits 31-24 sid 0-7 23-16 sid 8-15 15-08 svid 16-23 07-00 svid 24-31 name type reset by reset state function sid[15:0] r/wpb p1_rst 0 eeprom subsystem id values for subsystem id are vendor specific svid[15:0] r/wpb p1_rst 0 eeprom subsystem vendor id subsystem vendor ids are obtained from the pci sig and used to identify the vendor of the add-in board or subsystem.
12. register descriptions 261 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.9 pci-1 capability pointer register the cap_ptr indicates the register offset in pci c onfiguration space of the first capabilities pointer in the capabilities linked-list. this register is not implemente d in the secondary pci interface. register name: p1_cap register offset: 0x034 pci bits function pb bits 31-24 pci reserved 0-7 23-16 pci reserved 8-15 15-08 pci reserved 16-23 07-00 cap_ptr 0 0 24-31 name type reset by reset state function cap_ptr [7:0] r p1_rst 0xe4 capabilities pointer
12. register descriptions 262 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.10 pci-1 miscellaneous 1 register register name: p1_misc1 register offset: 0x03c pci bits function pb bits 31-24 max_lat 0-7 23-16 min_gnt 8-15 15-08 int_pin 16-23 07-00 int_line 24-31 p1_misc1 description name type reset by reset state function max_lat [7:0] r/w p1_rst 0 maximum latency this field specifies how often the device needs access to the pci bus. no special latency requirements min_gnt [7:0] r/w p1_rst 0 minimum grant this field indicates how long a master wants to retain bus ownership whenever it initiates a transaction. no special requirements int_pin [7:1] r p1_rst 0 interrupt pin (7 to 1) this field represents general purpose interrupt pins. interrupt pins are active low and, when configured as input, are sampled on three successive processor bus clock edges to ensure appropriate setting of a status bit. each pin is bidirectional, open drain, active low and level sensitive. the input/output character of each interrupt pin is controlled through a corresponding bit in the ?interrupt direction register? on page 347 . each pin can be configured as either an input or output. all pins are configured as inputs by default. int_pin [0] r/wpb p1_rst 1 eeprom interrupt pin this interrupt pin is used to enable pci interrupts. if this bit is not set, powerspan ii does not use pci interrupts. setting this bit enables a single function pci device to use inta#. 0 = the device does not use any pci interrupts 1 = the device uses inta_
12. register descriptions 263 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com int_line [7:0] r/w p1_rst 0 interrupt line this read/write interrupt line field is used to identify which of the system interrupt request lines on the interrupt controller the device?s interrupt request pin is routed to. p1_misc1 description name type reset by reset state function
12. register descriptions 264 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.11 pci-1 compact pci hot swap control and status register powerspan ii supports compactpci hot swap specification revision 2.0 and is a hot swap silicon device. this register controls compactpci hot swap support in powerspan ii. the hot swap functionality is enabled in the primary pci interface of powerspan ii. in the single pci powerspan ii the lone pci interface is enabled as primary, but in the dual pci powerspan ii only one of the two ports can be enabled as primary. this register is not implemente d in the secondary pci interface. register name: p1_hs_csr register offset: 0x0e4 pci bits function pb bits 31-24 pci reserved 0-7 23-16 ins ext pi loo 0 eim 0 8-15 15-08 nxt_ptr 16-23 07-00 cap_id 24-31 name type reset by reset state function ins r/write 1 to clear p1_rst 0 enum# status - insertion 1 = enum# asserted 0 = enum# negated ext r/write 1 to clear p1_rst 0 enum_ status - extraction 1 = enum# asserted 0 = enum# negated pi r p1_rst 0 programming interface programming interface bit indicates the programming interface supported by the board. powerspan ii implements a bit value of 0, which means ins, ext, loo, eim are supported. refer to the compactpci hot swap specification revision 2.0 for more information. 00 = ins, ext, loo, eim supported 01,10,11 = reserved loo r/w p1_rst 0 led on/off 1 = led on 0 = led off
12. register descriptions 265 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com eim r/w p1_rst 0 enum# signal mask 1 = mask signal 0 = enable signal nxt_ptr [7:0] r p1_rst 0xe8 or 0 next pointer if vpd_en bit is set in the ?miscellaneous control and status register? on page 318 and an external eeprom is detected, then this field reads back 0xe8. when the vpd_en bit in the misc_csr register is cleared or an external eeprom is not detected, this field reads back 0. cap_id [7:0] r p1_rst 0x06 capability id name type reset by reset state function
12. register descriptions 266 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.12 pci-1 vital product data capability register powerspan ii only supports vpd access from the pr imary pci interface. the secondary pci interface reads zero for vpd accesses. vpd writes have no effect. vpd can also be disabled when the nxt_ptr bit in the ?pci-1 compact pci hot swap control and status register? on page 264 register is 0. register name: p1_vpdc register offset: 0e8 pci bits function pb bits 31-24 f reserved 0-7 23-16 vpda 8-15 15-08 nxt_ptr 16-23 07-00 cap_id 24-31 name type reset by reset state function f r/w p1_rst 0 data transfer complete flag indicates when the transfer between the vpd data register and the eeprom is complete. software clears the bit to initiate a read and powerspan ii sets the bit when the read data is available in the vpd data register. software sets the bit to initiate a write and powerspan ii clears the bit to indicate when the data has been transferred. vpda [7:0] r/w p1_rst 0x00 vital product data address the 8-bit address specifies the vpd address offset for the vpd-read or vpd-write to the serial eeprom. when i2c chip select 0 is used for the vpd eeprom the vpd address translates a maximum of 64 bytes and 192 bytes are available for vpd. the first 64 bytes of vpd is vpd-read only, and the remaining 128 bytes ? 192 bytes if separate 256 byte eeprom used for vpd ? is vpd-read/write. nxt_ptr [7:0] r p1_rst 0x00 next pointer vpd is the last extended capabilities pointer cap_id [7:0] r p1_rst 0x03 capability id
12. register descriptions 267 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.13 pci-1 vital pr oduct data register this register is enabled when the vpd_en bit in the ?miscellaneous control and status register? on page 318 is set to 1. if it is disabled , the register always reads zero. vpd is also disabled when the nxt_ptr bit in the ?pci-1 compact pci hot swap contro l and status register? on page 264 register is 0. powerspan ii only supports vpd access from the pr imary pci interface. the secondary pci interface always reads zero for vpd accesses and vpd writes have no effect. register name: p1_vpdd register offset: 0x0ec pci bits function pb bits 31-24 vpd_data 0-7 23-16 vpd_data 8-15 15-08 vpd_data 16-23 07-00 vpd_data 24-31 name type reset by reset state function vpd_data [31:0] r/w p1_rst 0 vpd data
12. register descriptions 268 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.14 pci-1 target im age x control register this register contains th e control information for the powerspan ii pci 1 target image x. the image is enabled for decode when both img_en and bar_en are set. the bits in this register are not dynamic. do not alter these settings while transactions are being processed through powerspan ii. refer to ?translation address mapping? on page 293 for more information on dynamic address translation. register name: p1_tix_ctl register offset: 0x100, 0x110, 0x120, 0x130 pci bits function pb bits 31-24 img_en ta_en bar_ en md_en bs 0-7 23-16 mode dest mem_io rtt 8-15 15-08 gbl ci 0 wtt 16-23 07-00 pr keep end mra 0 rd_amt 24-31 name type reset by reset state function img_en r/w p1_rst 0 image enable the image enable bit is set by the following: ? non-zero write to the p1_bstx register ? register write to img_en the image enable is cleared by writing 0 to the img_en bit or writing a 0 to the ?pci target base address register? on page 259 . img_en will always read zero if p1_bstx is zero. 0 = disable 1 = enable ta_en r/w p1_rst 0 translation address enable when set, the translation address (p1_tix_taddr) replaces the upper bits of the pci x bus address. the new address is used on the destination bus. clearing the enable bit results in no address translation. 0 = disable 1 = enable
12. register descriptions 269 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com bar_en r/w p1_rst 1 eeprom pci base address register enable when this bit is set, the p1_bst x register is read/write and visible to pci bios configuration cycles. when this bit is disabled, the p1_bstx register is not visible in pci-1 configuration space and is read zero only. writes to p1_bstx have no effe ct when this bit is cleared. this effectively disables the powerspan ii p1_bstx image and powerspan ii does not request pci memory space for the image. if the user is clearing this bit, they must also clear p1_bstx. 0 = disable 1 = enable md_en r/w p1_rst 0 master decode enable enables master decode when the internal pci arbiter is in use ?when the p1_arb_en bit in the ?reset control and status register? on page 324 is set. if md_en is cleared, only the pci address and command are used for transaction decode. if md_en is set, the originating master is included in the transaction decode. a transaction is claimed only if it originates from the master(s ) specified in p1_tix_taddr. 0=disable 1=enable bs[3:0] r/w p1_rst 0 eeprom block size (64 kbyte * 2 bs ) the block size specifies the size of the image, address lines compared and address lines translated (see ta b l e 6 7 ). mode r/w p1_rst 0 image mode determines if the image is used to generate memory or io commands on pci. the mode is only applicable if the destination is the alternate pci bus. 0 = memory command generation 1 = i/o command generation or 4 byte memory read (see table 68 on page 272 ) dest r/w p1_rst 0 destination bus selects the destination bus for the transaction. 0 = processor bus 1 = pci-2 bus single pci powerspan ii: reserved processor bus is the only destination. name type reset by reset state function
12. register descriptions 270 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com mem_io r/w p1_rst 0 mem_io mode powerspan ii supports 4-byte reads. when this bit is set, i/o commands to the corresponding image generates memory read commands on the destination pci bus (py) with the same byte enables latched from the source bus transaction. if the destination of the transaction is the pb interface, a minimum 32-bit aligned, 4-byte read is generated on the processor bus. the mode bit and the mem_io bit work together to control the size of the transaction (see table 68 ). 0 = regular io mode 1 = enables 4 byte reads on the processor (60x) bus or 1,2,3 or 4 byte memory reads on the pci bus(es). the bus that the read occurs on is controlled by the dest bit. rtt[4:0] r/w p1_rst 0b01010 processor bus read transfer type (pb_tt[0:4]) selects the transfer type on the processor bus. the register bits rtt[4:0]/wtt[4:0] are mapped to pins pb_tt[0:4] 01010 = read gbl r/w p1_rst 0 global 0 = assert pb_gbl_ 1 = negate pb_gbl_ ci r/w p1_rst 0 cache inhibit 0 = assert pb_ci_ 1 = negate pb_ci_ wtt[4:0] r/w p1_rst 0b00010 processor bus write transfer type (pb_tt[0:4]) selects the transfer type on the processor bus. the register bits rtt[4:0]/wtt[4:0] are mapped to pins pb_tt[0:4] 00010 = write with flush prkeep r/w p1_rst 0 prefetch read keep data used to hold read data fetched beyond the initial pci read cycle. when set, subsequent read requests to the same image at the next address retrieves the read data directly from the switching fabric instead of causing the destination bus to fetch more data. the read data is invalidated when a read with a non-matching address occurs. 0 = disable 1 = enable name type reset by reset state function
12. register descriptions 271 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com bs: the block size specifies the size of the image, address lines co mpared and address lines translated. end[1:0] r/w p1_rst 0b10 endian conversion mode this bit sets the endian conversion mode. this field is only applicable if the destination is the processor bus. 00 = little-endian 01 = powerpc little-endian 10 = big-endian 11 = true little-endian mra r/w p1_rst 0 pci memory read alias to memory read multiple 0 = disabled 1 = enabled when set, the pci x target image x alias a pci memory read cycle to a pci memory read multiple cycle and prefetches the number of bytes specified in the rd_amt[2:0] field. when mra is cleared the target image prefetches 8 bytes when a pci memory read command is decoded. rd_amt[2:0] r/w p1_rst 0 prefetch size specifies the number of bytes the device prefetches for pci memory read multiple transactions claimed by the target image (see ta b l e 6 9 ). table 67: block size bs[3:0] block size address lines compared/translated 0000 64k ad31-ad16 0001 128k ad31-ad17 0010 256k ad31-ad18 0011 512k ad31-ad19 0100 1m ad31-ad20 0101 2m ad31-ad21 0110 4m ad31-ad22 0111 8m ad31-ad23 1000 16m ad31-ad24 1001 32m ad31-ad25 1010 64m ad31-ad26 name type reset by reset state function
12. register descriptions 272 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com mode: determines if the image is used to generate memory or io commands on pci. the mode is only applicable if the destination is the alternate pci bus. ? memory command mode: pci memory commands generated on pci-2. bursting is supported. prkeep and rd_amt[2:0] are only appl icable in memory command mode. ? io command mode causes pci io commands to be generated on pci-2. when the image is selected to perform io commands, transactions are limited to 4 bytes or less. a pci master initiated cycle attempting to burst to the image in this mode will be terminated with a target disconnect (retry) after every data beat. the mode bit and the mem_io bit work together to control the size of the transaction (see table 68 ). 1011 128m ad31-ad27 1100 256m ad31-ad28 1101 512m ad31-ad29 1110 1g ad31-ad30 1111 2g ad31 table 68: setting for mode and mem_io bits mode setting mem_io setting transaction size 0x a a. x means either 0 or 1. memory cycle (minimum 8 byte memory read) 1 0 i/o cycle 1 1 memory cycle (minimum 4 byte memory read) table 67: block size bs[3:0] block size address lines compared/translated
12. register descriptions 273 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com rd_amt[2:0]: the read amount setting determines differen t values to prefetch from the destination bus. table 69: read amount rd_amt[2:0] data fetched 000 8 bytes 001 16 bytes 010 32 bytes 011 64 bytes 100 128 bytes 101-111 reserved
12. register descriptions 274 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.15 pci-1 target image x translation address register m7-m1: these bits indicate wh ich external master(s) are qualified to access the image. the image supports master decode if the pc i arbiter is enabled (the p1_arb_en bit in the rst_csr register is set) and when the md_en bit in the p1_tix_ctl register is set. table 70 details external arbitration pins associated with bits m7-m1. the shaded combinations in the table identify external arbitration pins which can be used for pci-1, depending on the programming of the pci_m7, pci_m6,pci_m5 bits in the misc_csr register. register name: p1_tix_taddr register offset: 0x104, 0x114, 0x124, 0x134 pci bits function pb bits 31-24 taddr 0-7 23-16 taddr 8-15 15-08 powerspan ii reserved 16-23 07-00 m7 m6 m5 m4 m3 m2 m1 0 24-31 name type reset by reset state function taddr[15:0] r/w p1_rst 0 translation address (through substitution) when the ta_en bit in the p1_tix_ctl register is set, taddr[15:0] replaces the pci- 1 bus upper address bits. it replaces the upper address bits up to the size of the image. the taddr[15:0] field can be changed while transactions are being processed by powerspan ii. this is the only parameter that can be changed during a transaction. all other programmable parameters must stay constant during a transaction. m7-m1 r/w p1_rst 0 master select indicates which external master(s) are qualified to access the image. 0 = do not claim transactions generated by this master 1 = claim transactions generated by this master table 70: arbitration pin mapping register bit external arbitration pins m1 p1_req#[1]/p1_gnt#[1] m2 p1_req#[2]/p1_gnt#[2]
12. register descriptions 275 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com m3 p1_req#[3]/p1_gnt#[3] m4 p1_req#[4]/p1_gnt#[4] m5 pci_req#[5]/pci_gnt#[5] m6 pci_req#[6]/pci_gnt#[6] m7 pci_req#[7]/pci_gnt#[7] table 70: arbitration pin mapping register bit external arbitration pins
12. register descriptions 276 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.16 pci-1 to pci-2 configuration cycle information register this register is used to set up the address phase of a pci configurat ion cycle on pci-2. this register is not implemented in the single pci powerspa n ii and must be treated as reserved. type: for a configuration type 1 cycle ? with the type bit set to 1 ? an access of the pci-1 configuration data register performs a correspon ding configuration type 1 cycle on the pci-2 interface. during the address phase of the configurat ion type 1 cycle, the pci-2 address lines carry the values encoded in the p1_conf_info regi ster (p2_ad[31:0] = p1_conf_info[31:0]). register name: p1_conf_info register offset: 0x144 pci bits function pb bits 31-24 powerspan ii reserved 0-7 23-16 bus_num 8-15 15-08 dev_num func_num 16-23 07-00 reg_num 0 type 24-31 name type reset by reset state function bus_num [7:0] r/w p1_rst 0 bus number dev_num [4:0] r/w p1_rst 0 device number func_ num [2:0] r/w p1_rst 0 function number reg_num [5:0] r/w p1_rst 0 register offset type r/w p1_rst 0 configuration cycle type 0 = type 0 1 = type 1
12. register descriptions 277 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com for a configuration type 0 cycle ? with the type bit set to 0 ? an access of the pci configuration data register performs a corresponding config uration type 0 cycle on the pci-2 interface. programming the device number causes one of the upp er address lines, p2_ad[31:11], to be asserted during the address phase of the config uration type 0 cycle as defined in table 71 . the remaining address lines are: ? p2_ad[10:8] = func_num[2:0] table 71: pci-2 ad[31:11] lines assert ed during configuration type 0 cycles dev_num[4:0] p2_ad[31:11] 00000 0000 0000 0000 0001 0000 0 00001 0000 0000 0000 0010 0000 0 00010 0000 0000 0000 0100 0000 0 00011 0000 0000 0000 1000 0000 0 00100 0000 0000 0001 0000 0000 0 00101 0000 0000 0010 0000 0000 0 00110 0000 0000 0100 0000 0000 0 00111 0000 0000 1000 0000 0000 0 01000 0000 0001 0000 0000 0000 0 01001 0000 0010 0000 0000 0000 0 01010 0000 0100 0000 0000 0000 0 01011 0000 1000 0000 0000 0000 0 01100 0001 0000 0000 0000 0000 0 01101 0010 0000 0000 0000 0000 0 01110 0100 0000 0000 0000 0000 0 01111 1000 0000 0000 0000 0000 0 10000 0000 0000 0000 0000 0000 1 10001 0000 0000 0000 0000 0001 0 10010 0000 0000 0000 0000 0010 0 10011 0000 0000 0000 0000 0100 0 10100 0000 0000 0000 0000 1000 0 10101-11111 0000 0000 0000 0000 0000 0
12. register descriptions 278 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com ? p2_ad[7:2] = reg_num[5:0] ? p2_ad[1:0] = 00
12. register descriptions 279 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.17 pci-1 to pci-2 confi guration cycle data register a write to the configurati on data register from the pci-1 bus causes a configur ation write cycle to be generated on the pc i-2 interface. this is defined by the ?pci-1 to pci-2 configuration cycle information register? on page 276 (p1_conf_info). a read of th is register from the pci-1 bus causes a configuration read cycle to be generated on the pci-2 interface. th e pci bus configuration cycles generated by accessi ng the configuration data register are handled as a posted write or delayed read. a write to the pci configuration data register fr om the pci-2 interface or the processor bus has no effect. a read from pci-2 interface or th e processor bus returns undefined data. this register is not implemented in the single pc i powerspan ii and must be treated as reserved. register name: p1_conf_data register offset: 0x148 pci bits function pb bits 31-24 cdata 0-7 23-16 cdata 8-15 15-08 cdata 16-23 07-00 cdata 24-31 name type reset by reset state function cdata [31:0] r/w p1_rst 0 configuration data
12. register descriptions 280 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.18 pci-1 to pci-2 interrupt a cknowledge cycle generation register reading this register from the pci-1 bus causes an iack cycle to be generated on the pci-2 interface. the byte lanes enabled on the pci-2 bus are determ ined by p1_cbe#[3:0] of the pci-1 memory read cycle. the address on the pci-1 bus used to access the p1_iack register is passed directly over to the pci-2 bus during the pci iack cy cle. however, address informati on is ignored during pci iack cycles and has no effect. reads from this register behave as delayed transfers. this means that the pci-1 bus master is retried until the read data is latched from the pci-2 targ et. when the iack cycle completes on the pci-2 bus, the iack_vec[31:0] fi eld is returned as read da ta when the pci-1 bus mast er returns after the retry. writing to this register from the processor bus or either pci bus has no effect. reads from the pci-2 interface and processor bus return all zeros. this register is not implemented in the single pc i powerspan ii and must be treated as reserved. register name: p1_iack register offset: 0x14c pci bits function pb bits 31-24 iack_vec 0-7 23-16 iack_vec 8-15 15-08 iack_vec 16-23 07-00 iack_vec 24-31 name type reset by reset state function iack_vec [31:0] r p1_rst 0 pci iack cycle vector
12. register descriptions 281 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.19 pci-1 bus error cont rol and status register the pci-1 bus interface logs errors when it detect s a parity error, master -abort, target-abort, or maximum retry conditions register name: p1_errcs register offset: 150 pci bits function pb bits 31-24 powerspan ii reserved mes es 0-7 23-16 powerspan ii reserved 8-15 15-08 powerspan ii reserved 16-23 07-00 cmderr powerspan ii reserved 24-31 name type reset by reset state function mes r p1_rst 0 multiple error status indicates if multiple errors occur. the original error logging is not overwritten when mes is set. clearing es also clears the mes bit. 1 = a second error occurred before the first error could be cleared. es r/write 1 to clear p1_rst 0 error status when the es bit is set, it means an error has been logged and the contents of the cmderr[3:0] and paerr[31:0] of the p1_aerr register are valid. information in the log cannot be changed while es is set. clearing the es by writing 1 to the bit allows the error log registers to capture future errors. 0 = no error currently logged 1 = error currently logged cmderr [3:0] r p1_rst 0 pci command error log
12. register descriptions 282 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.20 pci-1 address error log register the pci-1 interface logs errors wh en it detects a parity error, master-abort, target-abort, or maximum retry conditions. register name: p1_aerr register offset: 0x154 pci bits function pb bits 31-24 paerr 0-7 23-16 paerr 8-15 15-08 paerr 16-23 07-00 paerr 24-31 name type reset by reset state function paerr [31:0] r p1_rst 0 pci address error log the address of a pci-1 bus transaction that generates an error condition is logged in this register. when the error occurs, the es bit in the ?pci-1 bus error control and status register? on page 281 is set, qualifying and freezing the contents of this register. this register logs additional errors only after the es bit in the p1_errcs register is cleared.
12. register descriptions 283 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.21 pci-1 miscellaneous c ontrol and status register register name: p1_misc_csr register offset: 0x160 pci bits function pb bits 31-24 powerspan ii reserved 0-7 23-16 powerspan ii reserved 8-15 15-08 bsreg_b ar_ en powerspan ii reserved max_retry 16-23 07-00 mac_ err powerspan ii reserved 24-31 name type reset by reset state function bsreg_bar_en r/w p1_rst 1 eeprom pci-1 registers image base address register enable. when this bit is cleared, the ?pci-1 register image base address register? on page 258 is not visible in pci-1 configuration space and reads zero. also, when this bit is cleared writes have no effect when this bit is cleared. when the p1_bsreg register is not visible in pci-1 configuration space, the powerspan ii pci-1 register image is disabled and powerspan ii does not request pci memory space for the image. 0=disable 1=enable max_retry[3:0] r/w p1_rst 0 maximum number of pci retry terminations 0000 = retry forever 0001 = 64 retries other - 2 24 retries mac_err r/w p1_rst 1 master abort configuration error mapping 0 = generate target abort when master abort occurs on pci-2 configuration cycles 1 = return all ones when master-abort occurs on pci-2 configuration cycles single pci powerspan ii: reserved
12. register descriptions 284 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.22 pci-1 bus arbiter control register powerspan ii?s pci-1 interface has dedicated support for four external pci masters. the user can assign up to three additional pci masters to the pci-1 arbiter by configuring the pci_m7 bit, the pci_m6 bit, and the pci_m5 in the ?miscellaneous control and status register? on page 318 . the powerspan ii pci-1 internal ar biter is enabled by a power-up optio n. when disabled, an external arbiter is used. the signals p1_req[1]_/p1_gnt[1]_ are used by the powers pan ii pci-1 master to arbitrate for access to the bus. the p1_arb_en bit in the ?reset control and status register? on page 324 specifies if the pci-1 arbiter is enabled or disabled. depending on the number of external masters supported, some of bits m4-m7 and combinations of bm_park are not applicable. programming these combinations result in unpred ictable powerspan ii behavior. register name: p1_arb_ctrl register offset: 0x164 pci bits function pb bits 31-24 powerspan ii reserved 0-7 23-16 status_bits 8-15 15-08 m7_pri m6_pri m5_pri m4_pri m3_pri m2_pri m1_pri ps_pri 16-23 07-00 powerspan ii reserved status_ en park bm_park 24-31 name type reset by reset state function status_ bits r/w p1_rst 0 operational status of pci master device x these series of bits are separated per master. there is one bit designated for each master and is separate from the others, but all eight are called status_bits[7:0]. the individual bits are set when a pci master does not respond to a grant given by the powerspan ii arbiter for 16 clock cycles. once this bit is set to 1 by the powerspan ii arbiter, the powerspan ii arbiter does not include the non-functioning pci master in the arbitration algorithm used by powerspan ii. when the bit is set to 0, the operating status of the pci master is functioning and it is included in the arbitration algorithm used by powerspan ii. 0 = functioning 1 = non-functioning
12. register descriptions 285 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com bm_park[2:0]: this field instructs the arb iter where to park the bus. the shaded combinations in table 72 identifies potential pci-1 external masters. their presence depends on the programming of the pci_m7,pci_m6,pci_m5 bits in the misc_csr register. mx_pri r/w p1_rst 0 arbitration level for pci master device x determines the arbitration priority level for pci master agents assigned to the pci-1 arbiter. 0 = low priority 1 = high priority ps_pri r/w p1_rst 0 arbitration level for powerspan ii 0 = low priority 1 = high priority status_en r/w p1_rst 0 enable monito ring of master by arbiter enables internal monitor of the powerspan ii pci arbiter. the monitor checks that no pci master waits longer than 16 pci clock cycles before starting a transaction. 0 = disabled 1 = enabled park r/w p1_rst 0 pci-1 bus parking algorithm when this bit is set the arbiter parks the pci-1 bus on the pci master programmed in the bm_park[2:0] field. when cleared the arbiter parks the pci-1 bus on the last pci master to be granted the bus. 0 = last master 1 = select master bm_park [2:0] r/w p1_rst 0 parked master this field instructs the arbiter where to park the bus. the shaded combinations in table 72 identifies potential pci-1 external masters. their presence depends on the programming of the pci_m7,pci_m6,pci_m5 bits in the ?miscellaneous control and status register? on page 318 register. table 72: parked pci master bm_park [2:0] parked pci master external pins 000 powerspan ii none 001 m1 p1_req#[1]/p1_gnt#[1] 010 m2 p1_req#[2]/p1_gnt#[2] name type reset by reset state function
12. register descriptions 286 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 011 m3 p1_req#[3]/p1_gnt#[3] 100 m4 p1_req#[4]/p1_gnt#[4] 101 m5 pci_req#[5]/pci_gnt#[5] 110 m6 pci_req#[6]/pci_gnt#[6] 111 m7 pci_req#[7]/pci_gnt#[7] table 72: parked pci master bm_park [2:0] parked pci master external pins
12. register descriptions 287 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.23 processor bus slave im age x control register this register contains the control information for the ?processor bus slave im age x control register? on page 287 . the bits in this register are not dyna mic. do not alter these settings while transactions are being processed through powerspan ii. refer to ?processor bus slave image x translation ad dress register? on page 292 for more information on dynamic address translation. register name: pb_six_ctl register offset: 0x200, 0x210, 0x220, 0x230, 0x240, 0x250, 0x260, 0x270 pci bits function pb bits 31-24 img_en ta_en md_en bs 0-7 23-16 mode dest mem_io powerspan ii reserved 8-15 15-08 powerspan ii reserved 16-23 07-00 prkeep end 0 0 rd_amt 24-31 name type reset by reset state function img_en r/w pb_rst 0 eeprom image enable the image enable bit is changed in the following ways: ? eeprom initialization ? register write to img_en the img_en is cleared by writing a zero to the bit. 0=disable 1=enable ta_en r/w pb_rst 0 eeprom translation address enable when set, the translation address ( ?processor bus slave image x translation address register? on page 292 ) replaces the upper bits of the processor bus address. clearing the enable results in no address translation. 0=disable 1=enable
12. register descriptions 288 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com md_en r/w pb_rst 0 eeprom master decode enable enables master decode when the processor bus arbiter is in use ? the processor bus arbiter enable bit, in the ?reset control and status register? on page 324 , is set. if md_en is cleared, only the processor bus address and transaction type are used for transaction decode. if md_en is set, the originating master is included in the transaction decode. a transaction is claimed only if it originates from the master(s) specified in ?processor bus slave image x translation address register? on page 292 . 0=disable 1=enable bs[4:0] r/w pb_rst 0 eeprom block size (4 kbyte*2 bs ) specifies the size of the image, address lines compared and address lines translated (see table 73 on page 289 ). mode r/w pb_rst 0 eeprom image mode determines if the image is used to generate memory or io commands on pci. 0 = memory command generation 1 = i/o command generation or 4 byte memory read (see table 74 on page 291 ) dest r/w pb_rst 0 eeprom destination bus selects the destination bus for the transaction. 0 = pci 1 bus 1 = pci-2 bus single pci powerspan ii: reserved pci-1 bus is the only destination. mem_io r/w pb_rst 0 mem_io mode powerspan ii supports 4-byte reads. when this bit is set, the memory read command to the corresponding image generates the memory read command on the destination pci bus with a minimum 32 bit aligned 4-byte read. the mode bit and the mem_io bit work together to control the size of the transaction (see table 74 on page 291 ). 0 = regular i/o mode 1 = enables 1,2,3, or 4 byte memory reads on the pci bus(es) name type reset by reset state function
12. register descriptions 289 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com bs: specifies the size of the image, address li nes compared and address lines translated. prkeep r/w pb_rst 0 eeprom prefetch read keep prefetch read keep stores prefetch data beyond an initial read. when set, subsequent read requests to the same image at the next address retrieves the read data directly from the switching fabric instead of causing either pci bus to fetch more data. the read data is invalidated when a read with a non-matching address occurs 0 = purge read data at end of transfer 1 = keep read data caution: the artry_en bit must be set to 1 in order for the powerspan ii prefetch keep feature to keep prefetched data. the artry_en bit is in the ?processor bus miscellaneous control and status register? on page 304 . end[1:0] r/w p1_rst 10b eeprom endian conversion mode selects the endian mapping. 00 = little-endian 01 = powerpc little-endian 10 = big-endian 11 = true little-endian rd_amt [2:0] r/w pb_rst 0 eeprom read prefetch amount amount of read data fetched from pci. if prkeep is not set, it is recommended limiting the rd_amt to 32-bytes (see table 75 on page 291 ). if the slave image is programmed to be in io mode (the mode bit in the ?processor bus slave image x control register? on page 287 set to 1 then the rd_amt is not used and a maximum of 4 bytes will be read from the pci bus. table 73: block size bs[4:0] block size address lines compared/translated 00000 4k a0-a19 00001 8k a0-a18 00010 16k a0-a17 00011 32k a0-a16 00100 64k a0-a15 00101 128k a0-a14 name type reset by reset state function
12. register descriptions 290 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com mode: determines if the image is used to generate memory or io commands on pci. ? memory command mode causes pci memory commands to be gene rated on pci. bursting is supported. prkeep and rd_amt[2:0] are only appl icable in memory command mode. ? io command mode causes pci io commands to be generated on pci. when the image is selected to perform io commands, transactions are limited to 4 bytes or less. a transaction attempting to move more than 4 bytes will cause a tea_ response. the tea_ can be suppressed by setting the pb_misc_csr[tea_en] bit. 00110 256k a0-a13 00111 512k a0-a12 01000 1m a0-a11 01001 2m a0-a10 01010 4m a0-a9 01011 8m a0-a8 01100 16m a0-a7 01101 32m a0-a6 01110 64m a0-a5 01111 128m a0-a4 10000 256m a0-a3 10001 512m a0-a2 10010 1g a0-a1 10011 2g a0 10100-11111 reserved reserved table 73: block size bs[4:0] block size address lines compared/translated
12. register descriptions 291 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the mode bit and the mem_io bit work together to control the size of the transaction (see table 74 ). prkeep: prefetch read keep stores prefetch data beyon d an initial read. when set, subsequent read requests to the same image at the next address retrieve s the read data directly from the switching fabric instead of causing either pci bus to fetch more data. the read data is invalidated when a read with a non-matching address occurs. rd_amt[2:0]: the read amount setting de termines different values to prefetch from pci. if prkeep is not set, it is recommended limiting the rd_amt to 32-bytes. if the slave image is programmed to be in io mode (the mode bit in the ?processor bus slave image x control register? on page 287 set to 1 then the rd_amt is not used and a maximum of 4 bytes will be read from the pci bus. table 74: setting for mode and mem_io bits mode setting mem_io setting transaction size 0x a a. x means either 0 or 1. memory cycle (minimum 8 byte memory read) 1 0 i/o cycle 1 1 memory cycle (1,2,3, or 4 byte memory reads on the pci bus(es)) the artry_en bit must be set to 1 in order for the powerspan ii prefetch keep feature to keep prefetched data. the artry_en bit is in the ?processor bus miscellaneous control and status register? on page 304 . table 75: read amount rd_amt[2:0] data fetched 000 8 bytes 001 16 bytes 010 32 bytes 011 64 bytes 100 128 bytes 101-111 reserved the eeprom load capability allows a pr ocessor on the processor bus to boot directly from a device on pci. only the control registers for processor bus slave image 0 are loaded from eeprom.
12. register descriptions 292 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.24 processor bus slave image x translation address register taddr : the translation address register replaces the processor bus address, up to the size of the image. taddr[31:12] replace the processor bus pb_a[0:19]. for example, if taddr[31:12] = 0x12345 and pb_six_ctl[bs]=0 (4 k image) and the address on the processor bus is pb_a[0:31] = 0x78563412, then the pci address becomes 0x12345412 register name: pb_six_taddr register offset: 0x204, 0x214, 0x224, 0x234, 0x244, 0x254, 0x264, 0x274 pci bits function pb bits 31-24 taddr 0-7 23-16 taddr 8-15 15-08 taddr powerspan ii reserved 16-23 07-00 powerspan ii reserved m3 m2 m1 0 24-31 name type reset by reset state function taddr[19:0] r/w pb_rst 0 eeprom translation address the translation address register replaces the processor bus address, up to the size of the image. taddr[31:12] replace the processor bus pb_a[0:19] (see table 76 on page 293 ). m3-m1 r/w pb_rst 0 eeprom master select these bits indicate which external master(s) are qualified to access the image. the image supports master decode if the processor bus arbiter is enabled ? the processor bus arbiter enable bit, in the ?reset control and status register? on page 324 , is set and when md_en bit in the ?processor bus slave image x control register? on page 287 is set. bit m3 represents the external master connected to pb_bg[3]_ and m1 represents the external master connected to pb_bg[1]_. 0=do not claim transactions generated by this master 1=claim transactions generated by this master
12. register descriptions 293 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the taddr[19:0] field can be changed while transact ions are being processed by powerspan ii. this is the only parameter that can be changed during a transaction. all othe r programmable parameters must stay constant during a transaction. m3-m1: these bits indicate whic h external master(s) are qualifie d to access the image. the image supports master decode if the processor bus arbiter is enabled ? the processor bus arbiter enable bit, in the ?reset control and stat us register? on page 324 , is set and when md_en bit in the pb_six_ctl is set. bit m3 represents the external master connected to pb_bg[3]_ and m1 represents the external master co nnected to pb_bg[1]_. table 76: translation address mapping pb_six_taddr[] processor bus address pb_a pb_six_ctl[bs] block size 31 0 10011 2g 31:30 0:1 10010 1g 31:29 0:2 10001 512m 31:28 0:3 10000 256m 31:27 0:4 01111 128m 31:26 0:5 01110 64m 31:25 0:6 01101 32m 31:24 0:7 01100 16m 31:23 0:8 01011 8m 31:22 0:9 01010 4m 31:21 0:10 01001 2m 31:20 0:11 01000 1m 31:19 0:12 00111 512k 31:18 0:13 00110 256k 31:17 0:14 00101 128k 31:16 0:15 00100 64k 31:15 0:16 00011 32k 31:14 0:17 00010 16k 31:13 0:18 00001 8k 31:12 0:19 00000 4k
12. register descriptions 294 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.25 processor bus slave imag e x base address register this register defines the lowest address of the slave image. the minimum image size is 4 kbyte as defined in bs fiel d in the pb_six_ctl. the initial write to this register sets the img_en bit in the ?processor bus slave image x control register? on page 287 . subsequent writes to this register will have no effect on the img_en bit. a base address of 0 is valid. register name: pb_six_baddr register offset: 0x208, 0x218, 0x228, 0x238, 0x248,0x 258, 0x268, 0x278 pci bits function pb bits 31-24 ba 0-7 23-16 ba 8-15 15-08 ba 0 0 0 0 16-23 07-00 powerspan ii reserved 24-31 name type reset by reset state function ba[19:0] r/w pb_rst 0 eeprom processor bus base address
12. register descriptions 295 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.26 processor bus register image base address register this register defines the processor bus address offset for powerspan ii internal registers. the register can be loaded by an external eeprom. a base address of 0 is valid. register name: pb_reg_baddr register offset: 0x280 pci bits function pb bits 31-24 ba 0-7 23-16 ba 8-15 15-08 ba powerspan ii reserved 16-23 07-00 powerspan ii reserved end 24-31 name type reset by reset state function ba[19:0] r/w pb_rst 0x30000 eeprom processor bus register base address the base address for the processor bus base address image represent the upper address bits (a[31:12]). the base address for the processor address bus at reset is 0x3000_0000. end r/w pb_rst 0 eeprom endian conversion mode the endian conversion mode for processor access to powerspan ii registers. 0 = big-endian 1 = powerpc little-endian
12. register descriptions 296 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.27 processor bus pci configurat ion cycle information register this register is used to set up the a ddress phase of a pci configuration cycle. type: for a configuration type 1 cycle ? with the type bit set to 1 ? an access of the pci configuration data register performs a correspondi ng configuration type 1 cycle on either pci bus. during the address phase of the configuration type 1 cycle, the pci address lines carry the values encoded in the pb_conf_info register (ad[31 :0] = pb_conf_info[31:0 ]). the destination (dest) field, in the pb_conf_info register, is an exception to this beca use it is zero on ad[24]. register name: pb_conf_info register offset: 0x290 pci bits function pb bits 31-240000000 dest 0-7 23-16 bus_num 8-15 15-08 dev_num func_num 16-23 07-00 reg_num 0 type 24-31 name type reset by reset state function dest r/w pb_rst 0 destination bus 0 = pci 1 1 = pci-2 dest r/w pb_rst 0 single pci powerspan ii: reserved pci-1 bus is the only destination. bus_num[7:0] r/w pb_rst 0 bus number dev_num[4:0] r/w pb_rst 0 device number func_num[2:0] r/w pb_rst 0 function number reg_num[5:0] r/w pb_rst 0 register number type r/w pb_rst 0 configuration cycle type 0 = type 0 1 = type 1
12. register descriptions 297 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com for a configuration type 0 cycle ? with the type bit set to 0 ? an access of the pci configuration data register performs a corresponding configura tion type 0 cycle on either pci bus. programming the device number causes the assertion of one of the upper address lines, ad[31:11], during the address phase of the configuration type 0 cycle. this is shown in table 77 . the remaining address lines are: ? ad[10:8] = func_num[2:0] table 77: pci ad[31:11] lines asserted during configuration type 0 cycles dev_num[4:0] ad[31:11] 00000 0000 0000 0000 0001 0000 0 00001 0000 0000 0000 0010 0000 0 00010 0000 0000 0000 0100 0000 0 00011 0000 0000 0000 1000 0000 0 00100 0000 0000 0001 0000 0000 0 00101 0000 0000 0010 0000 0000 0 00110 0000 0000 0100 0000 0000 0 00111 0000 0000 1000 0000 0000 0 01000 0000 0001 0000 0000 0000 0 01001 0000 0010 0000 0000 0000 0 01010 0000 0100 0000 0000 0000 0 01011 0000 1000 0000 0000 0000 0 01100 0001 0000 0000 0000 0000 0 01101 0010 0000 0000 0000 0000 0 01110 0100 0000 0000 0000 0000 0 01111 1000 0000 0000 0000 0000 0 10000 0000 0000 0000 0000 0000 1 10001 0000 0000 0000 0000 0001 0 10010 0000 0000 0000 0000 0010 0 10011 0000 0000 0000 0000 0100 0 10100 0000 0000 0000 0000 1000 0 10101-11111 0000 0000 0000 0000 0000 0
12. register descriptions 298 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com ? ad[7:2] = reg_num[5:0] ? ad[1:0] = 00 powerspan ii does not generate configur ation cycles to de vices connected to ad[15:11].
12. register descriptions 299 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.28 processor bus configur ation cycle data register a write to the configuration data register from th e processor bus causes a configuration write cycle to be generated on either pci bus as defined by the ?processor bus pci configuration cycle information register? on page 296 . a read of this register from the processor bus causes a configuration read cycle to be generated on either pci bus. th e pci bus configuration cycles generated by accessing the configuration data register is handled as a posted write or delayed read. the byte lanes enabled on the pci bus are determined by pb_siz[0:3] and pb_a[30:31] of the processor bus read or write cycle. a write to the pci configuration data register from th e either pci bus has no effect. a read from either pci bus is undefined. the end bit in the ?processor bus register image ba se address register? on page 295 selects the endian conversion scheme used fo r accesses to pci through this re gister. the definition of endian conversion scheme is for pci accesses, not register accesses. register name: pb_conf_data register offset: 0x294 pci bits function pb bits 31-24 cdata 0-7 23-16 cdata 8-15 15-08 cdata 16-23 07-00 cdata 24-31 name type reset by reset state function cdata[31:0] r/w pb_rst 0 configuration data
12. register descriptions 300 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.29 processor bus to pci-1 interrupt acknowledge cycle generation register this register is used to generate an interrupt ac knowledge cycle originating on the processor bus and destined for the pci-1 bus. reading this register from the processor bus causes an iack cycle to be generated on the pci bus. the byte lanes enabled on the pci bus are determined by pb_siz[0:3] and pb_a[30:31] of the processor bus read cycle. the address on the processor bus used to access the pb_p1_iack register is passed di rectly over to the pci bus during the pci iack cycle. however, address information is ignored during pci iack cycles, so this has no effect. if the address retry enable (art ry_en) bit is set, in the ?pci-1 miscellaneous 1 register? on page 262 , the processor bus master is retried until the read data is latched from the pci target. when the iack cycle completes on the pci-1 bus, the iack_v ec[31:0] field is return ed as read data when the processor bus master returns after the retry. writing to this register from the processor bus or ei ther pci bus has no effect. reads from the pci bus return all zeros. the end bit in the ?processor bus register image ba se address register? on page 295 selects the endian conversion scheme used fo r accesses to pci through this re gister. the definition of endian conversion scheme is for pci accesses, not register accesses. register name: pb_p1_iack register offset: 0x2a0 pci bits function pb bits 31-24 iack_vec 0-7 23-16 iack_vec 8-15 15-08 iack_vec 16-23 07-00 iack_vec 24-31 name type reset by reset state function iack_vec[31:0] r pb_rst 0 pci iack cycle vector
12. register descriptions 301 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.30 processor bus to pci-2 interrupt acknowledge cycle generation register this register is used to generate an interrupt ac knowledge cycle originating on the processor bus and destined for the pci-2 bus. reading this register from the processor bus causes an iack cycle to be generated on the pci bus. the byte lanes enabled on the pci bus are determined by pb_siz[0:3] and pb_a[30:31] of the processor bus read cycle. the address on the processor bus used to access the pb_p1_iack register is passed di rectly over to the pci bus during th e pci iack cycle. however this has no effect because address informat ion is ignored during pci iack cycles. if the address retry enable (artry_en)) bit is set, in the ?pci-1 miscellaneous 1 register? on page 262 , the processor bus master is retried until the read data is latched from the pci target. when the iack cycle completes on the pci-2 bus, the iack_v ec[31:0] field is return ed as read data when the processor bus master returns after the retry. writing to this register from the processor bus, or either pci bus, has no effect. reads from the pci bus return all zeros. the end bit in the ?processor bus register image ba se address register? on page 295 selects the endian conversion scheme used fo r accesses to pci through this re gister. the definition of endian conversion scheme is for pci accesses, not register accesses. this register is not implemented in the single pc i powerspan ii and must be treated as reserved. register name: pb_p2_iack register offset: 0x2a4 pci bits function pb bits 31-24 iack_vec 0-7 23-16 iack_vec 8-15 15-08 iack_vec 16-23 07-00 iack_vec 24-31 name type reset by reset state function iack_vec[31:0] r pb_rst 0 pci iack cycle vector
12. register descriptions 302 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.31 processor bus error co ntrol and status register the processor bus interface logs erro rs when it detects a maximum retry error, parity error or assertion of pb_tea_ conditions. register name: pb_errcs register offset: 0x2b0 pci bits function pb bits 31-24 powerspan ii reserved mes es 0-7 23-16 powerspan ii reserved 8-15 15-08 tt_err powerspan ii reserved 16-23 07-00 siz_err powerspan ii reserved 24-31 name type reset by reset state function mes r pb_rst 0 multiple error status determines if multip le errors occur. the processor bus error logs are not overwritten when mes is set. clearing es also clears mes. 1 = a second error occurred before the first error could be cleared. es r/write 1 to clear pb_rst 0 error status when the es bit is set, it means an error has been logged and the contents of the tt_err, siz_err and aerr are valid. information in the log cannot be changed while es is set. clearing the es by writing a one to the bit allows the error log registers to capture future errors. 0 = no error currently logged 1 = error currently logged tt_err[4:0] r pb_rst 0 processor bus transaction type error log siz_err[3:0] r pb_rst 0 processor bus siz field error log
12. register descriptions 303 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.32 processor bus address error log the processor bus interface logs erro rs when it detects a maximum retry error, parity error or assertion of pb_tea_ conditions. the address of a processor bus transaction that genera tes an error condition is logged in this register. when the error occurs, the es bit in the ?processor bus error control and status register? on page 302 is set, qualifying and freezing the co ntents of this register. this regist er logs additional errors only after the es bit is cleared. register name: pb_aerr register offset: 0x2b4 pci bits function pb bits 31-24 aerr 0-7 23-16 aerr 8-15 15-08 aerr 16-23 07-00 aerr 24-31 name type reset by reset state function aerr[31:0] r pb_rst 0 processor bus error log
12. register descriptions 304 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.33 processor bus miscellaneous control and status register register name: pb_misc_csr register offset: 0x2c0 pci bits function pb bits 31-24 powerspan ii reserved 0-7 23-16 powerspan ii reserved 8-15 15-08 powerspan ii reserved max_retry 16-23 07-00 ext cyc mac_ tea mode_ 7400 tea_en artry_ en dp_en ap_en parity 24-31 name type reset by reset state function max_retry [3:0] r/w pb_rst 0 maximum number of retries. except for 0000, all entries are multiples of 64 retries 0000 = retry forever 0001 = 64 retries 0010 = 128 retries 0011 = 192 retries, etc. extcyc r/w pb_rst 0 determines if the powerspan ii pb master is enabled to generate extended cycles (16 byte or 24 byte) this ability improves performance of powerquicc ii systems. the extcyc bit must be set to 0 in order to ensure compatibility with winpath and other powerpc devices. 0 = cannot generate extended cycle 1= can generate extended cycle mac_tea r/w pb_rst 1 master-abort configuration error mapping this bit controls the handling of a master-abort while a powerspan ii pci master is generating a configuration transaction initiated by a processor bus master. if mac_tea is cleared, the processor bus slave returns all ones to the initiating processor bus master. if mac_tea is cleared and tea_en is set to 1, the processor bus slave asserts pb_tea_ to terminate the transaction initiated by the processor. 0 = assert pb_tea_ when master-abort occurs on pci configuration cycles 1 = return all ?1s? when master-abort occurs on pci configuration cycles
12. register descriptions 305 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com artry_en: controls powerspan ii?s use of pb_artry_ during the servicing of transactions. when artry_en is set, the processor bus slave retries a processor (60x) bus master under the following conditions: ? register write while an external master connec ted to another powerspa n ii interface is doing a register write ? register read during i 2 c load ? posted write when no buffers are available ? read from pci-1 or pci-2 mode_7400 r/w pb_rst 1 determines if powerspan ii processor bus slave can accept misaligned data transfers defined for powerpc 7400. refer to table 24 on page 108 for a complete list of data transfers supported by powerspan ii. 0 = cannot accept powerpc 7400 misaligned transfers 1 = can accept powerpc 7400 misaligned transfers tea_en r/w pb_rst 1 suppress pb_tea_ generation when this bit is cleared, powerspan ii never asserts tea_. error conditions are signalled exclusively with interrupts. 0 = powerspan ii does not assert pb_tea_ 1 = powerspan ii asserts pb_tea_ artry_en r/w pb_rst 0 address retry enable 0 = pb slave never asserts pb_artry_ 1 = pb slave asserts pb_artry_ as required dp_en r/w pb_rst 0 data parity enable when cleared, the powerspan ii does not check the parity pins for the proper parity value. powerspan ii still drives out parity on master writes and slave read cycles. parity checking is disabled by default. 0 = data parity checking disabled 1 = data parity checking enabled ap_en r/w pb_rst 0 address parity enable when cleared, the powerspan ii does not check the parity pins for the proper parity value. powerspan ii still drives out parity on master writes and slave read cycles. parity checking is disabled by default. 0 = address parity checking disabled 1 = address parity checking enabled parity r/w pb_rst 0 parity 0 = odd parity 1 = even parity name type reset by reset state function
12. register descriptions 306 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com artry_en is cleared by default. the user will see improved pro cessor bus interface utilization by setting artry_en. the artry_en bit must be set to 1 in order for the powerspan ii prefetch keep feature to keep prefetched data. prefetch keep is enabled by setting the prkeep bit in the ?processor bus slave image x control register? on page 287 .
12. register descriptions 307 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.34 processor bus arbi ter control register the arbitration control register is used to control the pa rameters of the on-chi p processor bus arbiter. register name: pb_arb_ctrl register offset: 0x2d0 pci bits function ppc bits 31-24 powerspan ii reserved 0-7 23-16 powerspan ii reserved m3_en m2_en m1_en 0 8-15 15-08 powerspan ii reserved m3_pri m2_pri m1_pri ps_pri 16-23 07-00 powerspan ii reserved ts_dly park bm_park 24-31 name type reset by reset state function mx_en r/w pb_rst pwrup external master x enable when set, the arbiter recognizes address bus requests for this master. when cleared, the arbiter ignores address bus requests from this master (see table 78 on page 308 ). 0=external requests ignored 1=external requests recognized mx_pri r/w pb_rst 0 external master x priority level determines the arbitration priority for external masters. 0 = low priority 1 = high priority ps_pri r/w pb_rst 0 powerspan ii priority level 0 = low priority 1 = high priority ts_dly r/w pb_rst 0 controls when arbiter samples requests when set, the pb arbiter samples incoming requests two clocks after a ts_ signal is received. when cleared, the arbiter samples requests one clock after a ts_ signal is received. the default state is 0. an example application for this feature is some l2 caches hold the br_ signal after the ts_ signal starts. the powerspan ii arbiter could see this as a valid request and give the bus to the l2 cache when the bus was not requested. this bit delays when the pb arbiter samples the signal so a false bus request is not granted. 0 = sample clock after ts_ 1 = sample 2 clocks after ts_
12. register descriptions 308 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com mx_en : when set, the arbiter recognizes address bu s requests for this master. when cleared, the arbiter ignores address bus requests from this master. the default st ate for these bits is determined by the pwrup_boot option as defined by table 78 : bm_park : identifies the master to be parked (see table 79 ). park r/w pb_rst 0 bus park mode when set, the arbiter parks the address bus on the processor bus master programmed in the bm_park field. when cleared, the arbiter parks the address bus on the last processor bus master to be granted the bus. 0 = park on last bus master 1 = park on specific master bm_park r/w pb_rst 0 bus master to be parked identifies the master to be parked (see table 79 on page 308 ). 00 = powerspan ii 01 = external master 1 10 = external master 2 11 = external master 3 table 78: mx_en default state pwrup_boot selection rst_csr register m1_en m2_en m3_en boot pci pci_boot=1 0 0 0 boot processor bus pci_boot=0 1 0 0 table 79: parked processor bus master bm_park [1:0] parked processor bus master external pins 00 powerspan ii none 01 m1 pb_br[1]_/pb_bg[1]_ 10 m2 pb_br[2]_/pb_bg[2]_ 11 m3 pb_br[3]_/pb_bg[3]_ name type reset by reset state function
12. register descriptions 309 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.35 dma x source address register this register specifies the starting byte address on the source port for channel dmax. the register is programmed for direct mode dma or updated by the linked-list when loading the command packet the dmax_src_addr register is up dated during the dma tr ansaction. writing to this register while the dma is active has no ef fect. while the dma is active, this register provide status information on the progress of the transfer. register name: dmax_src_addr register offset: 0x304, 0x334, 0x 364, 0x394 pci bits function pb bits 31-24 saddr 0-7 23-16 saddr 8-15 15-08 saddr 16-23 07-00 saddr 24-31 name type reset by reset state function saddr[31:0] r/w g_rst 0 starting byte address on the source bus for the port defined by src_port field in the ?dma x transfer control register? on page 311 .
12. register descriptions 310 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.36 dma x destination address register this register specifies the startin g byte address on the destination por t for channel dmax. this register is programmed for a direct mode dma or programm ed by the linked-list wh en loading the command packet. the dmax_dst_addr register is updated during th e dma transaction. wri ting to this register while the dma is active has no effect. while the dma is active, this re gister provides status information on the progress of the transfer. register name: dmax_dst_addr register offset: 0x30c, 0x33c, 0x36c, 0x39c pci bits function pb bits 31-24 daddr 0-7 23-16 daddr 8-15 15-08 daddr 16-23 07-00 daddr 0 0 0 24-31 name type reset by reset state function daddr[31:3] r/w g_rst 0 starting byte address on the destination bus for the port defined by dst_port field in the ?dma x transfer control register? on page 311 . the lower three bits of the destination address is identical to the lower three bits of the source address (dmax_src_addr)
12. register descriptions 311 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.37 dma x transfer control register this register is used to specify parameters for channel dmax. it is programmed directly for direct mode dma or programmed by the linked-li st when loading the command packet. writing to this register while the dma is active ha s no effect. while the dma is active, this register provides status information on the progress of the transfer. register name: dmax_tcr register offset: 0x314, 0x344, 0x374, 0x3a4 pci bits function pb bits 31-24 src_port dst_port end 0 0-7 23-16 bc 8-15 15-08 bc 16-23 07-00 bc 24-31 name type reset by reset state function src_port [1:0] r/w g_rst 0 source port for dma transfer 00 = pci-1 01 = pci-2 10 = pb 11 = reserved single pci powerspan ii: 00 = pci-1 10 = pb 01, 11 = reserved dst_port [1:0] r/w g_rst 0 destination port for dma transfer 00 = pci-1 01 = pci-2 10 = pb 11 = reserved single pci powerspan ii: 00 = pci-1 10 = pb 01, 11 = reserved
12. register descriptions 312 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com end[1:0] r/w p1_rst 10 endian conversion mode selects the endian conversion mode for dma activity involving the processor bus and a pci interface. when the source and destination ports are the same, then the conversion mode is little-endian, regardless of the value of this bit. 00 = little-endian 01 = powerpc little-endian 10 = big-endian 11 = true little-endian bc[23:0] r/w g_rst 0 byte count when the initial value of the byte count is non-zero in linked-list mode, the dma starts with a direct mode transfer. after the direct mode transfer has completed, the dma channel begins processing the linked-list. the field is updated during the dma transaction. name type reset by reset state function
12. register descriptions 313 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.38 dma x command packet pointer register this register specifies the 32-byte aligned address of the next command packet in the linked-list for channel dmax. it is programmed by powerspan ii from the linked-list wh en loading the command packet. the dmax_cpp register is updated at the start of a linked-list transfer and remains constant throughout the transfer. writing to this register while the dma is active has no effect. for a direct mode dma transfer, this re gister does not need to be programmed. register name: dmax_cpp register offset: 0x31c, 0x34c, 0x37c, 0x3ac pci bits function pb bits 31-24 ncp 0-7 23-16 ncp 8-15 15-08 ncp 16-23 07-00 ncp powerspan ii reserved last 24-31 name type reset by reset state function ncp[31:5] r/w g_rst 0 next command packet address. points to a 32-byte aligned memory location of a linked-list on the port specified by the cp_port bit in the dmax_attr register. last r/w g_rst 0 last item 0 = more items in linked list 1 = last item in linked list
12. register descriptions 314 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.39 dma x general control and status register this register contains ge neral control and status in formation for channel dma x . this register is not part of a linked-list command packet.. writing to the chain and off bits while the dma is active has no effect. register name: dmax_gcsr register offset: 0x320, 0x350, 0x380, 0x3b0 pci bits function pb bits 31-24 go chain 0 0 0 stop_ req halt_ req 00-7 23-16 dact dbs dbs_ en off 8-15 15-08 0 0 p1_err p2_err pb_err stop halt done 16-23 07-00 0 0 p1_err_ en p2_err_ en pb_err_ en stop_ en halt_ en done_e n 24-31 name type reset by reset state function go write 1 to set g_rst 0 dma go bit 0 = no effect, 1 = begin dma transfer chain r/w g_rst 0 dma chaining 0 = dma direct mode 1 = dma linked-list mode stop_req write 1 to set g_rst 0 dma stop request 0 = no effect 1 = stop dma when all buffered data has been written halt_req write 1 to set g_rst 0 dma halt request 0 = no effect 1 = halt dma at completion of current command packet dact r g_rst 0 dma active 0 = not active 1 = active
12. register descriptions 315 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com dbs[1:0] r/w g_rst 0 dma block size (when dbs_en is set to 1) controls the byte size of transactions generated by the dma channel. the dbs_en bit must be set to 1 in order for the dbs functionality to be enabled. 00=32 bytes 01=16 bytes 10=8 bytes 11=4 bytes dbs_en r/w g_rst 0 dma block size enable provides programmable control over the byte size of transactions generated by the dma channel. the byte size is based on values programmed into dbs[1:0]. 0 = not active 1 = active off r/w g_rst 0 dma channel off counter (number of pb clocks) provides programmable control over the amount of source bus traffic generated by the dma channel. the channel will interleave source bus transfers with a period of idle processor bus clocks where no source bus requests are generated. when source and destination ports are different, 256 bytes of source bus traffic occur before the idle period. if source and destination ports are the same, 64 bytes of source bus traffic occur before the idle period. this helps prevent powerspan ii from interfering with processor bus instruction fetches. 000 = 0 001 = 128 010 = 256 011 = 512 100 = 1024 101 = 2048 110 = 4096 111 = 8192 p1_err r/write 1 to clear g_rst 0 pci-1 bus error 0 = no error 1 = error p2_err r/write 1 to clear g_rst 0 pci-2 bus error 0 = no error 1 = error single pci powerspan ii: reserved name type reset by reset state function
12. register descriptions 316 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com pb_err r/write 1 to clear g_rst 0 processor bus error 0 = no error 1 = error stop r/write 1 to clear g_rst 0 dma stopped flag 0 = not stopped 1 = stopped halt r/write 1 to clear g_rst 0 dma halted flag 0 = not halted 1 = halted done r/write 1 to clear g_rst 0 dma done flag the done bit is set in the following cases: ? completion of direct mode dma ? completion of linked-list dma the dma will not proceed until the done, and all other status bits, are cleared 0 = transfer not done 1 = transfer done p1_err_en r/w g_rst 0 primary pci error interrupt enable 0 = no interrupt 1 = enable interrupt p2_err_en r/w g_rst 0 normal pci error interrupt enable 0 = no interrupt 1 = enable interrupt single pci powerspan ii: reserved pb_err_en r/w g_rst 0 processor bus error interrupt enable 0 = no interrupt 1 = enable interrupt stop_en r/w g_rst 0 dma stop interrupt enable 0 = no interrupt 1 = enable interrupt halt_en r/w g_rst 0 dma halt interrupt enable 0 = no interrupt 1 = enable interrupt done_en r/w g_rst 0 dma done interrupt enable 0 = no interrupt 1 = enable interrupt name type reset by reset state function
12. register descriptions 317 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.40 dma x attr ibutes register this register contains ad ditional parameters for dma channel x. it is not part of a linked-list command packet. register name: dmax_attr register offset: 0x324, 0x354, 0x384, 0x3b4 pci bits function pb bits 31-24 cp_port 0 gbl_ ci_ powerspan ii reserved 0-7 23-16 powerspan ii reserved rtt 8-15 15-08 powerspan ii reserved wtt 16-23 07-00 powerspan ii reserved 24-31 name type reset by reset state function cp_port [1:0] r/w g_rst 0 command packet port 00 = pci-1 01 = pci-2, 10 = pb 11 = reserved single pci powerspan ii: 00 = pci-1 10 = pb 01, 11 = reserved pb_gbl_ r/w g_rst 0 processor bus global 0 = assert pb_gbl_ 1 = negate pb_gbl_ pb_ci_ r/w g_rst 0 processor bus cache inhibit 0 = assert pb_ci_ 1 = negate pb_ci_ rtt[4:0] r/w g_rst 01010 processor bus read transfer type pb_tt[0:4] selects the transfer type on the processor bus. the register bits rtt[4:0]/wtt[4:0] are mapped to pins pb_tt[0:4]. 01010 = read wtt[4:0] r/w g_rst 00010 processor bus write transfer type pb_tt[0:4] selects the transfer type on the processor bus. the register bits rtt[4:0]/wtt[4:0] are mapped to pins pb_tt[0:4]. 00010 = write with flush
12. register descriptions 318 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.41 miscellaneous cont rol and status register register name: misc_csr register offset: 0x400 pci bits function pb bits 31-24 tundra_dev_id 0-7 23-16 tundra_ver_id 8-15 15-08 vpd_en vpd_cs bar_ eq_0 reserved eload_opt 16-23 07-00 p1_lock out p2_lock out powerspan ii reserved pci_arb _cfg pci_m7 pci_m6 pci_m5 24-31 name type reset by reset state function tundra_dev_id[7:0] r g_rst 0x00 idt internal device id 0x01 single pci powerspan ii tundra_ver_id[7:0] r g_rst 0x02 idt internal version id powerspan ii = 02 (original powerspan = 01) vpd_en r/w g_rst 0 eeprom pci vital product data. enables pci vital product data (vpd) as described in the ?i2c/eeprom? on page 127 . when enabled, the vpd registers in the pci interface that has been designated as primary are used to access pci vital product data. 0=disabled 1=enabled vpd_cs[2:0] r/w g_rst 0 eeprom pci vital product data eeprom chip select. bar_eq_0 r/w g_rst 0 eeprom base address equivalent to 0x00000 this bit enables a value of 0x00000 for px base address registers.
12. register descriptions 319 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com eload_opt[1:0] r g_rst 0 eeprom eeprom load option identifies the load option selected in the first byte of the power-up eeprom. 00=do not load 01=short load 10=long load 11=reserved p1_lockout r/write 1 to clear g_rst 1 eeprom pci-1 lockout when set, all configuration and memory register space accesses from pci are retried. the px_lockout bit must be cleared for all memory space accesses to the powerspan ii?s pci target images. 0=not set 1=set p2_lockout r/write 1 to clear g_rst 1 eeprom pci-2 lockout when set, all configuration and memory register space accesses from pci are retried. the px_lockout bit must be cleared for all memory space accesses to the powerspan ii?s pci target images. 0=not set 1=set single pci powerspan ii: reserved pci_arb_cfg write 1 to set g_rst 0 eeprom pci arbiter pins configured when set, this bit enables recognition of external master requests on pci_req#[7:5] (see table 80 on page 320 ) 0=floating pci arbiter pins not yet configured 1=floating pci arbiter pins configured single pci powerspan ii: reserved pci_m7 r/w g_rst 0 eeprom pci arbiter master 7 0=powerspan ii pci-1 arbiter 1=powerspan ii pci-2 arbiter single pci powerspan ii: reserved pci_m6 r/w g_rst 0 eeprom pci arbiter master 6 0=powerspan ii pci-1 arbiter 1=powerspan ii pci-2 arbiter single pci powerspan ii: reserved name type reset by reset state function
12. register descriptions 320 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com px_lockout: when set, all configuration and memory register space accesses from pci are retried. the px_lockout bit must be cleared for all me mory space accesses to the powerspan ii?s pci target images. the px_lockout bit must be cleared before th e corresponding pci target image claims a transaction. the bit is cleared by an agent on the processor bus or by eeprom load. the bit is cleared automatically by powerspan ii when the pwrup_boot option is set to pci. pci_arb_cfg : when set, this bit enables recogni tion of external master requests on pci_req#[7:5]. the user must set this bit after completing configuration all of the powerspan ii floating pci arbitration pins wi th bits pci_m7, pci_m6 and pc i_m5. when pci_arb_cfg is not set, requests from external masters conn ected to pci_req#[7 :5] are ignored. initialization of pci_arb_cfg is not required for the single pci powerspan ii because pci_req#[7:5]/pci_gnt#[7:5] are de dicated to the pci-1 interface. pci_mx: each of these pci master bits must be ex plicitly initialized by the user to indicate which powerspan ii pci arbiter should service the pair of pci_req#/pci_gnt# pins. initialization occurs through eeprom load or a register write. table 80 indicates register bit to arbitration pin mappings: the pci_mx bits do not affect the behavior of the single pci powerspan ii because pci_req#[7:5]#/pci_gnt#[7:5] are dedicated to the pci-1 interface. pci_m5 r/w g_rst 0 eeprom pci arbiter master 5 0=powerspan ii pci-1 arbiter 1=powerspan ii pci-2 arbiter single pci powerspan ii: reserved powerspan ii does not terminate the cycle when the px_lockout bit is not cleared during a memory space access to the pci target imag es. if powerspan ii does not terminate the cycle, the pci bus experi ences a deadlock condition. table 80: arbitration pin mappings bit arbitration pins pci_m5 pci_req#[5]/pci_gnt#[5] pci_m6 pci_req#[6]/pci_gnt#[6] pci_m7 pci_req#[7]/pci_gnt#[7] name type reset by reset state function
12. register descriptions 321 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.42 clock control register powerspan ii does not use the tune bits for adju sting the pll parameters. this register does not effect pll performance. this register does not effect the functionality or performance of powerspan ii. this register makes the device backwards compatib le with the powerspan ii device. register name: clock_ctl register offset: 0x404 pci bits function pb bits 31-24 pb_tune 0-7 23-16 p1_tune 8-15 15-08 p2_tune 16-23 07-00 powerspan ii reserved 24-31 name type reset by reset state function pb_tune[7:0] r g_rst eeprom pb pll tune bits tune bits for the processor bus pll. the reset value is a function of the system level applied to the pb_fast external pin. the reset values are: ? pb_tune[7:2] = 000100 ? pb_tune[1] = ~pb_fast ? pb_tune[0] = 1 p1_tune[7:0] r g_rst eeprom pci-1 pll tune bits tune bits for the pci-1 pll. the reset value is a function of the system level applied to the p1_m66en external pin. the reset values are: ? p1_tune[7:1] = 0001001 ? p1_tune[0] = ~p1_m66en p2_tune[7:0] r g_rst eeprom pci-2 pll tune bits tune bits for the pci-2 pll. the reset value is a function of the system level applied to the p2_m66en external pin. the reset values are: ? p2_tune[7:1] = 0001001 ? p2_tune[0] = ~p2_m66en
12. register descriptions 322 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.43 i 2 c/eeprom interface contro l and status register this register supports the powerspan ii i 2 c/eeprom interface. an i 2 c bus cycle is initiated by writing to this register. software must wait for the act bit to be zero before starting a new i 2 c cycle. when the act bit is 1, writes to this register have no effect and the data field is undefined. the pci vpd eeprom chip select (vpd_cs) bit, in the ?miscellaneous control and status register? on page 318 , selects the eeprom where vpd resides. if vpd_cs is 000b, then vpd starts at address offset 0x40 of the firs t eeprom. for all other values of vpd_cs, vpd starts at address offset 0x00 of the specified eeprom. both the act bit and the err bit are upda ted five pb clocks after a pb write completion (pb_ta asserted) register name: i2c_csr register offset: 0x408 pci bits function pb bits 31-24 addr 0-7 23-16 data 8-15 15-08 dev_code cs rw 16-23 07-00 act err powerspan ii reserved 24-31 name type reset by reset state function addr[7:0] r/w g_rst 0 specifies i 2 c device address to be accessed. data[7:0] r/w g_rst 0 specifies the required data for a write. holds the data at the end of a read. dev_code[3:0] r/w g_rst 1010 device select. i 2 c 4-bit device code. cs[2:0] r/w g_rst 0 chip select rw r/w g_rst 0 0=read 1=write
12. register descriptions 323 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com act r g_rst 0 i 2 c interface active the act bit is set under of the following conditions: ?i 2 c interface is busy servicing a read or write as a result of a write to this register ?i 2 c interface is busy loading registers at the end of reset ?i 2 c interface is busy accessing pci vital product data 0=not active 1=active err r/write 1 to clear g_rst 0 error 0=no error 1=error condition name type reset by reset state function
12. register descriptions 324 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.44 reset control and status register this register contains th e read-only bits that specify all powers pan ii power-up options and status of a number of pins that are norma lly fixed for each application. register name: rst_csr register offset: 0x40c pci bits function pb bits 31-24 pb_rst_ dir pb_arb_ en pb_fast pci_ boot powerspan ii reserved 0-7 23-16 p1_rst_ dir p1_arb_ en p1_m66 en powerspan ii reserved p1_r64_ en p1_d64 8-15 15-08 p2_rst_ dir p2_arb_ en p2_m66 en powerspan ii reserved pri_pci 16-23 07-00 power-sp an ii rsvd 7400_ mode bypass_ en eload powerspan ii reserved 24-31 name type reset by reset state function pb_rst_dir r g_rst pwrup sta tus of pb_rst_dir pin. pb_arb_en r g_rst p wrup processor bus arbiter enable. 0=disabled power-up option 1=enabled power-up option pb_fast r g_rst pwrup processor bus clock frequency selection indicates the latched value of the pb_fast pin. this bit is used to optimally configure the processor bus interface pll for the desired operating frequency. 0=25 mhz to 50 mhz 1=50 mhz to 100 mhz pci_boot r g_rst pwrup pci boot 0=boot from processor bus 1=boot from pci p1_rst_dir r g_rst pwrup sta tus of p1_rst_dir pin. p1_arb_en r g_rst pwrup pci-1 arbiter enable 0=disabled power-up option 1=enabled power-up option
12. register descriptions 325 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com p1_m66en r g_rst pwrup pci-1 clock frequency selection indicates the latched value of the p1_m66en pin. this bit is used to optimally configure the pci-1 interface pll for the desired operating frequency. 0=25 mhz to 33 mhz 1=33 mhz to 66 mhz p1_r64_en r g_rst pwrup p1_req64# output enable. 0=powerspan ii does not assert p1_req64# at reset 1=powerspan ii does assert p1_req64# at reset to indicate the presence of a 64-bit p1_ad[] bus p1_d64 r g_rst pwrup pci-1 databus width indicates the width of the databus to which the pci-1 interface is connected. this is determined by the level on p1_req64# at the negation of p 1_rst#, or by the level on p1_64en# (see table 3 on page 33 ). 0=connected to 32-bit ad bus 1=connected to 64-bit ad bus p2_rst_dir r g_rst pwrup status of p2_rst_dir pin. single pci powerspan ii: reserved p2_arb_en r g_rst pwrup pci-2 arbiter enable. 0=disabled power-up option 1=enabled power-up option single pci powerspan ii: reserved p2_m66en r g_rst pwrup pci-2 clock frequency selection indicates the latched value of the p2_m66en pin. this bit is used to optimally configure the pci-2 interface pll for the desired operating frequency. 0=25 mhz to 50 mhz 1=33 mhz to 66 mhz single pci powerspan ii: reserved pri_pci r g_rst pwrup designated primary pci bus. 0=pci-1 is primary 1=pci-2 is primary single pci powerspan ii: reserved name type reset by reset state function
12. register descriptions 326 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 7400_mode r g_rst pwrup 7400 mode enable when enabled, the pb arbiter qualifies bus grants before issuing a grant to a pb master. when disabled, the pb arbiter issues a grant to a pb master and it is expected that the pb master receiving the grant qualifies the grant. 0=disabled power-up option 1=enabled power-up option bypass_en r g_rst pwrup phase locked loop bypass enable indicates the setting of this power-up option. if this bit is set, the user has elected to bypass all powerspan ii pll?s. this bit supports slow speed emulation of a powerspan ii based system. 0=disabled power-up option 1=enabled power-up option eload r g_rst pwrup eeprom load after reset. 0=eeprom load not enabled 1=eeprom load enabled name type reset by reset state function
12. register descriptions 327 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.45 interrupt status register 0 this register is one of two interrupt status registers. isr0 is used primarily fo r normal operating status. when set, each bit of this register indicates the corresponding interru pt source is active. register name: isr0 register offset: 0x410 pci bits function pb bits 31-24 isr1_ac tv 0 i2o_hos t i2o_iop dma3 dma2 dma1 dma0 0-7 23-16 p2_hw p1_hw int5_ hw int4_ hw int3_ hw int2_ hw int1_ hw int0_ hw 8-15 15-08 db7 db6 db5 db4 db3 db2 db1 db0 16-23 07-00 mbox7 mbox6 mbox5 mbox4 mbox3 mbox2 mbox1 mbox0 24-31 name type reset by reset state function isr1_actv r g_rst 0 indicates an interrupt status bit is set in isr1 register. this bit is a logical or of all the status bits in the isr1 register. when any status bit in isr1 is set, isr1_actv is set. when all bits of the isr1 register are cleared, isr1_actv is cleared. this bit is useful in determining whether or not to read the isr1 register to determine the source of the interrupt. i2o_host r g_rst 0 interrupt asserted to the i2o host to indicate that the outbound post list fifo contains mfas of messages for the host to process. this bit is an alias for the i2o outbound post list status register located at offset 0x030 of the i2o target image. i2o_iop r/write 1 to clear g_rst 0 interrupt to embedded powerpc to indicate that the inbound post list fifo contains mfas of messages for the embedded powerpc to process. dmax r/write 1 to clear g_rst 0 set when dmax generates an interrupt. see dmax_gcsr register for details. p1_hw r/write 1 to clear g_rst 0 pci-1 hardware interrupt. set when a level interrupt is detected on the pci-1 inta# pin. p2_hw r/write 1 to clear g_rst 0 pci-2 hardware interrupt. set when a level interrupt is detected on the pci-2 inta# pin. single pci powerspan ii: reserved
12. register descriptions 328 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com int0_hw r/write 1 to clear g_rst 0 hardware interrupt. set when a level interrupt is detected on the int[0]_ pin. int1_hw r/write 1 to clear g_rst 0 hardware interrupt. set when a level interrupt is detected on the int[1]_ pin. int2_hw r/write 1 to clear g_rst 0 hardware interrupt. set when a level interrupt is detected on the int[2]_ pin. int3_hw r/write 1 to clear g_rst 0 hardware interrupt. set when a level interrupt is detected on the int[3]_ pin. int4_hw r/write 1 to clear g_rst 0 hardware interrupt. set when a level interrupt is detected on the int[4]_ pin. int5_hw r/write 1 to clear g_rst 0 hardware interrupt. set when a level interrupt is detected on the int[5]_ pin. db7-db0 r/write 1 to clear g_rst 0 set when a doorbell register is written to in the ier register. mbox[7:0] r/write 1 to clear g_rst 0 set when a mailbox is written to. name type reset by reset state function
12. register descriptions 329 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.46 interrupt status register 1 this register is one of two interrupt status regi sters. isr1 is organized with error conditions in powerspan ii. register name: isr1 register offset: 0x414 pci bits function pb bits 31-24 isr0_ac tv powerspan ii reserved pb_p1_r etry pb_p2_r etry pb_pb_r etry 00-7 23-16 pb_p1_e rr pb_p2_e rr pb_pb_e rr pb_a_pa r pb_p1_d _par pb_p2_d _par pb_pb_d _par 08-15 15-08 p2_p1_e rr p2_pb_e rr p2_p2_e rr p2_a_ par p2_p1_r etry p2_pb_r etry p2_p2_r etry 0 16-23 07-00 p1_p2_e rr p1_pb_e rr p1_p1_e rr p1_a_pa r p1_p2_r etry p1_pb_r etry p1_p1_r etry 0 24-31 name type reset by reset state function isr0_actv r g_rst 0 indicates an interrupt status bit is set in isr0 register. this bit is a logical or of all the status bits in the isr0 register. if any register is se t, isr0_actv is set. when all bits of the isr0 register are cleared, isr0_actv is cleared. pb_p1_ retry r/write 1 to clear g_rst 0 processor bus max retry error. maximum number of retries detected. the cycle was initiated/destined to the pci 1 bus. pb_p2_ retry r/write 1 to clear g_rst 0 processor bus max retry error. maximum number of retries detected. the cycle was initiated/destined to the pci-2 bus. single pci powerspan ii: reserved pb_pb_retry r/write 1 to clear g_rst 0 processor bus max retry error. maximum number of retries detected during processor bus to processor bus dma. pb_p1_err r/write 1 to clear g_rst 0 processor bus interface asserted/received pb_tea_. the cycle was initiated/destined to the pci-1 bus. pb_p2_err r/write 1 to clear g_rst 0 processor bus interface asserted/received pb_tea_. the cycle was initiated/destined to the pci-2 bus. single pci powerspan ii: reserved pb_pb_err r/write 1 to clear g_rst 0 processor bus interface asserted/received pb_tea_ during processor bus to processor bus dma.
12. register descriptions 330 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com pb_a_par r/write 1 to clear g_rst 0 processor bus address parity error detected. pb_p1_d_par r/write 1 to clear g_rst 0 processor bus data parity error detected. the cycle was initiated/destined to the pci 1 bus. pb_p2_d_par r/write 1 to clear g_rst 0 processor bus data parity error detected. the cycle was initiated/destined to the pci-2 bus. single pci powerspan ii: reserved pb_pb_d_par r/write 1 to clear g_rst 0 processor bus data parity error detected during processor bus to processor bus dma. p2_p1_err r/write 1 to clear g_rst 0 pci-2 interface detected an error. the p2_csr error bits must be checked for the source of the error. the cycle was initiated/destined to the pci 1 bus. single pci powerspan ii: reserved p2_pb_err r/write 1 to clear g_rst 0 pci-2 interface detected an error. the p2_csr error bits must be checked for the source of the error. the cycle was initiated/destined to the processor bus. single pci powerspan ii: reserved p2_p2_err r/write 1 to clear g_rst 0 pci-2 interface detected an error during p2 to p2 dma. 2p: reserved p2_a_par r/write 1 to clear g_rst 0 pci-2 interface detected an address parity error. 2p: reserved p2_p1_ retry r/write 1 to clear g_rst 0 pci-2 master received too many retries. the cycle was initiated from the pci 1 bus. 2p: reserved p2_pb_ retry r/write 1 to clear g_rst 0 pci-2 master received too many retries. the cycle was initiated from the processor bus. 2p: reserved p2_p2_ retry r/write 1 to clear g_rst 0 pci-2 master received too many retries during p2 to p2 dma. 2p: reserved name type reset by reset state function
12. register descriptions 331 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com p1_p2_err r/write 1 to clear g_rst 0 pci-1 interface detected an error. the p1_csr error bits must be checked for the source of the error. the cycle was initiated/destined to the pci-2 bus. 2p: reserved p1_pb_err r/write 1 to clear g_rst 0 pci-1 interface detected an error. the p1_csr error bits must be checked for the source of the error. the cycle was initiated/destined to the processor bus. p1_p1_err r/write 1 to clear g_rst 0 pci-1 interface detected an error during p1 to p1 dma. p1_a_par r/write 1 to clear g_rst 0 pci-1 interface detected an address parity error. p1_p2_ retry r/write 1 to clear g_rst 0 pci-1 master received too many retries. the cycle was initiated from the pci-2 bus. 2p: reserved p1_pb_retry r/write 1 to clear g_rst 0 pci-1 master received to o many retries. the cycle was initiated from the processor bus. p1_p1_retry r/write 1 to clear g_rst 0 pci-1 master received too many retries during pci-1 to pci-1 dma. name type reset by reset state function
12. register descriptions 332 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.47 interrupt enable register 0 each bit, when set, allows the co rresponding active status bit in isr0 to generate an interrupt on an external pin. the external pin is determined by the interrupt mapping registers and the interrupt direction register. register name: ier0 register offset: 0x418 pci bits function pb bits 31-24 powerspan ii reserved i2o_hos t_mask i2o_iop_ en dma3_en dma2_en dma1_en dma0_en 0-7 23-16 p2_hw_e n p1_hw_e n int5_hw _en int4_hw _en int3_hw _en int2_hw _en int1_hw _en int0_hw _en 8-15 15-08 db7_en db6_en db5_en db4_en d b3_en db2_en db1_en db0_en 16-23 07-00 mbox7_e n mbox6_e n mbox5_e n mbox4_e n mbox3_e n mbox2_e n mbox1_e n mbox0_e n 24-31 name type reset by reset state function i2o_host_ma sk r/w g_rst 0 i2o_host interrupt mask this bit is an alias for the i2o register opl_im[op_ism] used to mask interrupts associated with the i2o outbound queue. 0=interrupt enabled 1=interrupt masked i2o_iop_en r/w g_rst 0 i2o_iop interrupt enable dmax_en r/w g_rst 0 dmax interrupt enable p1_hw_en r/w g_rst 0 pci 1 hardware interrupt enable p2_hw_en r/w g_rst 0 pci-2 hardware interrupt enable 2p: reserved int0_hw_en r/w g_rst 0 int[0]_ hardware interrupt enable int1_hw_en r/w g_rst 0 int[1]_ hardware interrupt enable int2_hw_en r/w g_rst 0 int[2]_ hardware interrupt enable int3_hw_en r/w g_rst 0 int[3]_ hardware interrupt enable int4_hw_en r/w g_rst 0 int[4]_ hardware interrupt enable int5_hw_en r/w g_rst 0 int[5]_ hardware interrupt enable
12. register descriptions 333 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com dbx_en write 1 to set g_rst 0 writing a one to this register sets the doorbell register in the isr0 register. this causes the corresponding doorbell bit in the isr0 register to be set. in order to clear the doorbell interrupt, the isr0 status bit must be cleared. mboxx_en r/w g_rst 0 mailbox interrupt enable name type reset by reset state function
12. register descriptions 334 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.48 interrupt enable register 1 each bit, when set, allows the co rresponding active status bit in isr1 to generate an interrupt on an external pin. the external pin is determined by the interrupt mapping registers and the interrupt direction register. register name: ier1 register offset: 0x41c pci bits function pb bits 31-24 powerspan ii reserved pb_p1_r etry_en pb_p2_r etry_en pb_pb_r etry_en 00-7 23-16 pb_p1_e rr_en pb_p2_e rr_ en pb_pb_e rr_en pb_a_pa r_en pb_p1_d _par_en pb_p2_d _par_en pb_pb_d _par_en 08-15 15-08 p2_p1_e rr_ en p2_pb_e rr_ en p2_p2_e rr_ en p2_a_pa r_en p2_p1_r etry_en p2_pb_r etry_en p2_p2_r etry_en 0 16-23 07-00 p1_p2_e rr_ n p1_pb_e rr_en p1_p1_e rr_en p1_a_pa r_en p1_p2_r etry_en p1_pb_r etry_en p1_p1_r etry_en 0 24-31 name type reset by reset state function pb_p1_retry_ en r/w g_rst 0 processor bus max retry counter enable. the cycle was initiated/destined to the pci-1 bus. pb_p2_ retry_en r/w g_rst 0 processor bus max retry error enable. the cycle was initiated/destined to the pci-2 bus. 2p: reserved pb_pb_retry r/w g_rst 0 processor bus max retry counter enable. processor bus to processor bus dma. pb_p1_err_e n r/w g_rst 0 processor bus error enable. the cycle was initiated/destined to the pci-1 bus. pb_p2_err_e n r/w g_rst 0 processor bus error enable. the cycle was initiated/destined to the pci-2 bus. 2p: reserved pb_pb_err_e n r/w g_rst 0 processor bus error enable. processor bus to processor bus dma. pb_a_par_en r/w g_rst 0 processor bus address parity error enable
12. register descriptions 335 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com pb_p1_d_par_ en r/w g_rst 0 processor bus data parity error enable. the cycle was initiated/destined to the pci-1 bus. pb_p2_d_ par_en r/w g_rst 0 processor bus data parity error enable. the cycle was initiated/destined to the pci-2 bus. 2p: reserved pb_pb_d_ par_en r/w g_rst 0 processor bus data parity error enable. processor bus to processor bus dma. p2_p1_err_en r/w g_rst 0 pci-2 error enable. the cycle was initiated/destined to the pci 1 bus. 2p: reserved p2_pb_err_e n r/w g_rst 0 pci-2 error enable. the cycle was initiated/destined to the processor bus. 2p: reserved p2_p2_err_en r/w g_rst 0 pci-2 error enable.pci-2 to pci-2 dma. 2p: reserved p2_a_par_ en r/w g_rst 0 pci-2 address parity error enable. 2p: reserved p2_p1_ retry_en r/w g_rst 0 pci-2 max retry enable. the cycle was initiated/destined to the pci-1 bus. 2p: reserved p2_pb_ retry_en r/w g_rst 0 pci-2 max retry enable. the cycle was initiated/destined to the processor bus. 2p: reserved p2_p2_ retry_en r/w g_rst 0 pci-2 max retry enable. pci-2 to pci-2 dma. 2p: reserved p1_p2_err_en r/w g_rst 0 pci-1 error enable. the cycle was initiated/destined to the pci-2 bus. 2p: reserved p1_pb_err_e n r/w g_rst 0 pci-1 error enable. the cycle was initiated/destined to the processor bus. name type reset by reset state function
12. register descriptions 336 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com p1_p1_err_en r/w g_rst 0 pci-1 error enable. pci-1 to pci-1 dma. p1_a_par_en r/w g_rst 0 pci-1 address parity error enable. p1_p2_ retry_en r/w g_rst 0 pci-1 max retry enable. the cycle was initiated/destined to the pci-2 bus. 2p: reserved p1_pb_retry_ en r/w g_rst 0 pci-1 max retry enable. the cycle was initiated/destined to the processor bus. p1_p1_retry_ en r/w g_rst 0 pci-1 max retry enable. pci-1 to pci-1 dma. name type reset by reset state function
12. register descriptions 337 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.49 interrupt map register mail box each map field assigns an interrupt output pin to the correspondi ng interrupt source. table 81 describes the mapping of interrupt sources to the external interrupt pi ns. the shaded entries indicate unsupported combinations for the single pci powerspan ii. register name: imr_mbox register offset: 0x420 pci bits function pb bits 31-24 mbox7_map 0 mbox6_map 0 0-7 23-16 mbox5_map 0 mbox4_map 0 8-15 15-08 mbox3_map 0 mbox2_map 0 16-23 07-00 mbox1_map 0 mbox0_map 0 24-31 name type reset by reset state function mbox7_map[2:0] r/w g_rst 0 map mailbox #7 to an interrupt pin. mbox6_map[2:0] r/w g_rst 0 map mailbox #6 to an interrupt pin. mbox5_map[2:0] r/w g_rst 0 map mailbox #5 to an interrupt pin. mbox4_map[2:0] r/w g_rst 0 map mailbox #4 to an interrupt pin. mbox3_map[2:0] r/w g_rst 0 map mailbox #3 to an interrupt pin. mbox2_map[2:0] r/w g_rst 0 map mailbox #2 to an interrupt pin. mbox1_map[2:0] r/w g_rst 0 map mailbox #1 to an interrupt pin. mbox0_map[2:0] r/w g_rst 0 map mailbox #0 to an interrupt pin. table 81: mapping definition map field interrupt pin 000 p1_inta# 001 p2_inta# 010 int[0]_ 011 int[1]_ 100 int[2]_
12. register descriptions 338 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 101 int[3]_ 110 int[4]_ 111 int[5_ table 81: mapping definition map field interrupt pin
12. register descriptions 339 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.50 interrupt map register doorbell each map field assigns an interrupt output pin to the correspondi ng interrupt source. table 81 on page 337 defines the mapping definitions. register name: imr_db register offset: 0x424 pci bits function pb bits 31-24 db7_map 0 db6_map 0 0-7 23-16 db5_map 0 db4_map 0 8-15 15-08 db3_map 0 db2_map 0 16-23 07-00 db1_map 0 db0_map 0 24-31 name type reset by reset state function db7_map[2:0] r/w g_rst 0 map doorbell #7 to an interrupt pin db6_map[2:0] r/w g_rst 0 map doorbell #6 to an interrupt pin db5_map[2:0] r/w g_rst 0 map doorbell #5 to an interrupt pin db4_map[2:0] r/w g_rst 0 map doorbell #4 to an interrupt pin db3_map[2:0] r/w g_rst 0 map doorbell #3 to an interrupt pin db2_map[2:0] r/w g_rst 0 map doorbell #2 to an interrupt pin db1_map[2:0] r/w g_rst 0 map doorbell #1 to an interrupt pin db0_map[2:0] r/w g_rst 0 map doorbell #0 to an interrupt pin
12. register descriptions 340 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.51 interrupt map register dma each map field assigns an interrupt output pin to the correspondi ng interrupt source. table 81 on page 337 defines the mapping definitions. register name: imr_dma register offset: 0x428 pci bits function pb bits 31-24 powerspan ii reserved 0-7 23-16 powerspan ii reserved 8-15 15-08 dma3_map 0 dma2_map 0 16-23 07-00 dma1_map 0 dma0_map 0 24-31 name type reset by reset state function dma3_map[2:0] r/w g_rst 0 map dma #3 to an interrupt pin dma2_map[2:0] r/w g_rst 0 map dma #2 to an interrupt pin dma1_map[2:0] r/w g_rst 0 map dma #1 to an interrupt pin dma0_map[2:0] r/w g_rst 0 map dma #0 to an interrupt pin
12. register descriptions 341 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.52 interrupt map register hardware this register assigns an interrupt output pin to the correspondi ng interrupt source. all sources are associated with errors det ected by the pci-1 interface. each map field assigns an interrupt output pin to the correspondi ng interrupt source. table 81 on page 337 defines the mapping definitions register name: imr_hw register offset: 0x42c pci bits function pb bits 31-24 p2_hw_map 0 p1_hw_map 0 0-7 23-16 int5_hw_map 0 int4_hw_map 0 8-15 15-08 int3_hw_map 0 int2_hw_map 0 16-23 07-00 int1_hw_map 0 int0_hw_map 0 24-31 name type reset by reset state function p1_hw_map[2:0] r/w g_rst 0 map pci-1 har dware interrupt to an interrupt pin p2_hw_map[2:0] r/w g_rst 0 map pci-2 hardware interrupt to an interrupt pin 2p: reserved int5_hw_map[2:0] r/w g_rst 0 map int[5]_ hardware interrupt to an interrupt pin int4_hw_map[2:0] r/w g_rst 0 map int[4]_ hardware interrupt to an interrupt pin int3_hw_map[2:0] r/w g_rst 0 map int[3]_ hardware interrupt to an interrupt pin int2_hw_map[2:0] r/w g_rst 0 map int[2]_ hardware interrupt to an interrupt pin int1_hw_map[2:0] r/w g_rst 0 map int[1]_ hardware interrupt to an interrupt pin int0_hw_map[2:0] r/w g_rst 0 map int[0]_ hardware interrupt to an interrupt pin
12. register descriptions 342 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.53 interrupt ma p register pci-1 each map field assigns an interrupt output pin to the correspondi ng interrupt source. table 81 on page 337 defines the mapping definitions. register name: imr_p1 register offset: 0x430 pci bits function pb bits 31-24 p1_p2_err_map 0 p1_p b_err_map 0 0-7 23-16 p1_p1_err_map 0 p1_a_par_map 0 8-15 15-08 p1_p2_retry_map 0 p1_pb_retry_map 0 16-23 07-00 p1_p1_retry_map powerspan ii reserved 24-31 name type reset by reset state function p1_p2_err_map[2:0 ] r/w g_rst 0 map pci-1 errors to an interrupt pin 2p: reserved p1_pb_err_map[2:0 ] r/w g_rst 0 map pci-1 errors to an interrupt pin p1_p1_err_map[2:0 ] r/w g_rst 0 map pci-1 errors to an interrupt pin. pci-1 to pci-1 dma. p1_a_par_map [2:0] r/w g_rst 0 map pci-11 address parity errors to an interrupt pin p1_p2_retry_ map[2:0] r/w g_rst 0 map pci-1 max retry error to an interrupt pin 2p: reserved p1_pb_retry_ map[2:0] r/w g_rst 0 map pci-1 max retry error to an interrupt pin p1_p1_retry_ map[2:0] r/w g_rst 0 map pci-1 max retry error to an interrupt pin. pci-1 to pci-1 dma.
12. register descriptions 343 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.54 interrupt map register pci-2 this register assigns an interrupt output pin to the correspondi ng interrupt source. all sources are associated with errors det ected by the pci-2 interface. table 81 on page 337 defines the mapping definitions. this register is not implemented in the single pc i powerspan ii and must be treated as reserved. register name: imr_p2 register offset: 434 pci bits function pb bits 31-24 p2_p1_err_map 0 p 2_pb_err_map 0 0-7 23-16 p2_p2_err_map 0 p2_a_par_map 0 8-15 15-08 p2_p1_retry_map 0 p2_pb_retry_map 0 16-23 07-00 p2_p2_retry_map powerspan ii reserved 24-31 i name type reset by reset state function p2_p1_err[2:0] r/w g_rst 0 map pci-2 errors to an interrupt pin p2_pb_err[2:0] r/w g_rst 0 map pci-2 errors to an interrupt pin p2_p2_err_map[2:0] r/w g_rst 0 map pci-2 errors to an interrupt pin. pci-2 to pci-2 dma. p2_a_par_map[2:0] r/w g_rst 0 map pci-2 address parity errors to an interrupt pin p2_p1_retry_map[2:0] r/w g_rst 0 map pci-2 max retry error to an interrupt pin p2_pb_retry_map[2:0] r/w g_rst 0 map pci-2 max retry error to an interrupt pin p2_p2_retry_map[2:0] r/w g_rst 0 map pci-2 max retry error to an interrupt pin. pci-2 to pci-2 dma.
12. register descriptions 344 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.55 interrupt map re gister processor bus this register assigns an interrupt output pin to the correspondi ng interrupt source. all sources are associated with errors detected by the processor bus interface. table 81 on page 337 defines the mapping definitions. register name: imr_pb register offset: 0x438 pci bits function pb bits 31-24 pb_p1_err_map 0 pb_p2_err_map 0 0-7 23-16 pb_pb_err_map 0 pb_a_par_map 0 8-15 15-08 pb_p1_d_par_map 0 pb_p2_d_par_map 0 16-23 07-00 pb_pb_d_par_map powerspan ii reserved 24-31 i name type reset by reset state function pb_p1_err_map[2:0] r/w g_rst 0 map processor bus error to an interrupt pin pb_p2_err_map[2:0] r/w g_rst 0 map processor bus error to an interrupt pin 2p: reserved pb_pb_err_map[2:0] r/w g_rst 0 map proce ssor bus error to an interrupt pin. processor bus to processor bus dma. pb_a_par_map[2:0] r/w g_rst 0 map proce ssor bus address parity error to an interrupt pin pb_p1_d_par_map[2:0] r/w g_rst 0 map processor bus data parity error to an interrupt pin pb_p2_d_par_map[2:0] r/w g_rst 0 map processor bus data parity error to an interrupt pin 2p: reserved pb_pb_d_par_map[2:0] r/w g_rst 0 map processor bus data parity error to an interrupt pin. processor bus to processor bus dma.
12. register descriptions 345 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.56 interrupt map regi ster two processor bus this register maps processor bus maximum retry errors to interrupt pins. max retry errors that are mapped include pci-1, pci-2 and processor bus. register name: imr2_pb register offset: 0x43c pci bits function pb bits 31-24 pb_p1_retry_map 0 pb_p2_retry_map 0 0-7 23-16 pb_pb_retry_map powerspan ii reserved 8-15 15-08 powerspan ii reserved 16-23 07-00 powerspan ii reserved 24-31 name type reset by reset state function pb_p1_retry_ map[2:0] r/w g_rst 0 map processor bus max retry errors to an interrupt pin pb_p2_retry_ map[2:0] r/w g_rst 0 map processor bus max retry errors to an interrupt pin single pci powerspan ii reserved pb_pb_retry_ map[2:0] r/w g_rst 0 map processor bus max retry errors to an interrupt pin. processor bus to processor bus dma.
12. register descriptions 346 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.57 interrupt map re gister miscellaneous each map field assigns an interrupt output pin to the correspondi ng interrupt source. table 81 on page 337 defines the mapping definitions. register name: imr_misc register offset: 0x440 pci bits function pb bits 31-24 i2o_iop_map 0 i2o_host_map 0 0-7 23-16 powerspan ii reserved 8-15 15-08 powerspan ii reserved 16-23 07-00 powerspan ii reserved 24-31 imr_misc description name type reset by reset state function i2o_host_map [2:0] r/w g_rst 0 map i2o host interrupt to an interrupt pin this field must be configured to route the interrupt source to the interrupt pin on powerspan ii?s primary pci interface. i2o_iop_map[2:0] r/w g_rst 0 map i2o iop interrupt to an interrupt pin
12. register descriptions 347 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.58 interrupt direction register this register controls the directio n of the corresponding interrupt pin. the direction can be to be an input or output. register name: idr register offset: 0x444 pci bits function pb bits 31-24 p2_hw_d ir p1_hw_d ir int5_hw _dir int4_hw _dir int3_hw _dir int2_hw _dir int1_hw _dir int0_hw _dir 0-7 23-16 powerspan ii reserved 8-15 15-08 powerspan ii reserved 16-23 07-00 powerspan ii reserved 24-31 name type reset by reset state function p2_hw_dir r/w g_rst 0 eeprom p2_inta _ direction 0 = input 1 = output 2p: reserved p1_hw_dir r/w g_rst 0 eeprom p1_inta_ direction 0 = input 1 = output int5_hw_dir r/w g_rst 0 eeprom int[5]_ interrupt direction 0 = input 1 = output int4_hw_dir r/w g_rst 0 eeprom int[4]_ interrupt direction 0 = input 1 = output int3_hw_dir r/w g_rst 0 eeprom int[3]_ interrupt direction 0 = input 1 = output int2_hw_dir r/w g_rst 0 eeprom int[2]_ interrupt direction 0 = input 1 = output
12. register descriptions 348 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com int1_hw_dir r/w g_rst 0 eeprom int[1]_ interrupt direction 0 = input 1 = output int0_hw_dir r/w g_rst 0 eeprom int[0]_ interrupt direction 0 = input 1 = output name type reset by reset state function
12. register descriptions 349 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.59 mailbox x register this register is the general purpose mailbox register . when interrupts are enabled in the ier0 register, writes to any byte of this register cause an interr upt. the interrupt can be mapped to any of powerspan ii?s interrupt pins. this mapping is set in the imr_mbox register. register name: mboxx register offset: 0x450, 0x454, 0x458, 0x45c, 0x460, 0x464, 0x468, 0x46c pci bits function pb bits 31-24 mboxx 0-7 23-16 mboxx 8-15 15-08 mboxx 16-23 07-00 mboxx 24-31 name type reset by reset state function mboxx [31:0] r/w g_rst 0 mailbox x
12. register descriptions 350 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.60 semaphore 0 register when a semx is 0, this semaphore can be obtained by writing a 1 to the semx bit with a unique tag tagx. if on a subsequent read, the semx bit is set and the tagx field contains the same unique tag, then the semaphore has been obtained successfully. to release a semaphore, write a 0 to the semx bi t and the same tag that was used to obtain the semaphore. if the tag is different from the tag that is in the register, then the write will have no effect. access to a single semaphore in this regi ster requires a by te-wide transaction. register name: sema0 register offset: 0x470 pci bits function pb bits 31-24 sem3 tag3 0-7 23-16 sem2 tag2 8-15 15-08 sem1 tag1 16-23 07-00 sem0 tag0 24-31 name type reset by reset state function sem3 r/w g_rst 0 semaphore 3 tag3[6:0] r/w g_rst 0 tag 3 sem2 r/w g_rst 0 semaphore 2 tag2[6:0] r/w g_rst 0 tag 2 sem1 r/w g_rst 0 semaphore 1 tag1[6:0] r/w g_rst 0 tag 1 sem0 r/w g_rst 0 semaphore 0 tag0[6:0] r/w g_rst 0 tag 0
12. register descriptions 351 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.61 semaphore 1 register if a semx is 0, this semaphore can be obtained by writing a 1 to the semx bit with a unique tag tagx. if on a subsequent read, the semx bit is set and the tagx field contains the sa me unique tag, then the semaphore has been obtained successfully. to release a semaphore, write a 0 to the semx bi t and the same tag that was used to obtain the semaphore. if the tag is different from the tag that is in the register, then the write will have no effect. access to a single semaphore in this regi ster requires a byte-wide transaction. register name: sema1 register offset: 0x474 pci bits function pb bits 31-24 sem7 tag7 0-7 23-16 sem6 tag6 8-15 15-08 sem5 tag5 16-23 07-00 sem4 tag4 24-31 name type reset by reset state function sem7 r/w g_rst 0 semaphore 7 tag7[6:0] r/w g_rst 0 tag 7 sem6 r/w g_rst 0 semaphore 6 tag6[6:0] r/w g_rst 0 tag 6 sem5 r/w g_rst 0 semaphore 5 tag5[6:0] r/w g_rst 0 tag 5 sem4 r/w g_rst 0 semaphore 4 tag4[6:0] r/w g_rst 0 tag 4
12. register descriptions 352 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.62 pci i2o target image control register this register contains the control in formation for the powerspan ii pci i 2 o target image. the lower 4 kbytes of the image provide the i 2 o shell interface - inbound and outbound queues and the host interrupt status and mask registers. i 2 o message frames are accessible above the 4-kbyte boundary. the queues and the message frames reside in memory connected to the processor bus. all pci transactions claimed by the ima ge are destined fo r the processor bus the following parameters do not affect pr ocessor bus transactions generated by i 2 o shell accesses: ? ta_en: no address translation for i 2 o shell accesses ? prkeep: no read keep for i 2 o shell accesses ?end ? rd_amt: prefetch amount fixed at 8 bytes for i 2 o shell accesses. register name: pci_ti2o_ctl register offset: 0x500 pci bits function pb bits 31-24 img_en ta_en bar_en 0 bs 0-7 23-16 powerspan ii reserved rtt 8-15 15-08 gbl ci 0 wtt 16-23 07-00 prkeep end mra 0 rd_amt 24-31 name type reset by reset state function img_en r/w pri_rst 0 image enable the image enable bit can be changed with the following actions: ? initial write to the ba field in the ?pci-1 i2o target image base address register? on page 257 ? register write to img_en the image enable is cleared by writing a zero to img_en or writing zero to the ba field in the px_bsi2o. this effectively disables i2o functionality. 0 = disable 1 = enable
12. register descriptions 353 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com ta_en r/w pri_rst 0 translation address enable when set, the translation address (taddr[15:0]) field, in the ?pci i2o target image translation address register? on page 356 replaces the upper bits of the pci bus address. the new address is used on the processor bus. clearing the enable will result in no address translation. 0 = disable 1 = enable bar_en r/w pri_rst 0 eeprom pci base address register enable when this bit is enabled the ?pci-1 i2o target image base address register? on page 257 is read/write. when this bit is disabled the register is not visible and reads zero only. writes to px_bsi2o have no effect when this bit is cleared. this bit must be enabled for pci bios configuration in order to map powerspan ii pci i2o target image into memory space. 0 = disable 1 = enable bs[3:0] r/w pri_rst 0 eeprom block size (64 kbyte * 2 bs ) specifies the size of the image, address lines compared and address lines translated (see table 82 on page 354 ). rtt[4:0] r/w pri_rst 0b01010 processor bus read transaction type (pb_tt[0:4]) 01010 = read gbl r/w pri_rst 0 global 0=assert pb_gbl_ 1=negate pb_gbl_ ci r/w pri_rst 0 cache inhibit 0=assert pb_ci_ 1=negate pb_ci_ wtt[4:0] r/w pri_rst 0b00010 processor bus write transaction type (pb_tt[0:4]) 00010=write with flush name type reset by reset state function
12. register descriptions 354 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com bs: specifies the size of the image, address li nes compared and address lines translated. prkeep r/w pri_rst 0 prefetch read keep data this bit is used to hold read data is fetched beyond the initial pci read cycle. when set, subsequent read requests to the same image at the next address retrieves the read data directly from the switching fabric instead of causing the destination bus to fetch more data. the read data is invalidated when a read with a non-matching address occurs. 0 = disable 1 = enable end[1:0] r/w pri_rst 10b endian conversion mode this selects the endian conversion mode. 00 = little-endian 01 = powerpc little-endian 10 = big-endian 11 = true little-endian mra r/w pri_rst 0 pci memory read alias to mrm when set, the pci i2o target image will alias a pci memory read cycle to a pci memory read multiple cycle and prefetches the number of bytes specified in the rd_amt[2:0] field. when mra is the target image prefetches 8 bytes when a pci memory read cycle is decoded and claimed. 0 = disabled 1 = enabled rd_amt[2:0] r/w pri_rst 0 prefetch size specifies the number of bytes the device will prefetch for pci memory read multiple transactions claimed by the target image (see table 83 on page 355 ) table 82: block size bs[3:0] block size address lines compared/translated 0000 64k ad31-ad16 0001 128k ad31-ad17 0010 256k ad31-ad18 0011 512k ad31-ad19 0100 1m ad31-ad20 name type reset by reset state function
12. register descriptions 355 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com rd_amt[2:0]: the read amount setting determines differen t values to prefetch from the destination bus (see table 83 on page 355 ). 0101 2m ad31-ad21 0110 4m ad31-ad22 0111 8m ad31-ad23 1000 16m ad31-ad24 1001 32m ad31-ad25 1010 64m ad31-ad26 1011 128m ad31-ad27 1100 256m ad31-ad28 1101 512m ad31-ad29 1110 1g ad31-ad30 1111 2g ad31 10100-11111 reserved reserved table 83: read amount rd_amt[2:0] data fetched 000 8 bytes 001 16 bytes 010 32 bytes 011 64 bytes 100 128 bytes 101-111 reserved table 82: block size bs[3:0] block size address lines compared/translated
12. register descriptions 356 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.63 pci i2o target image translation address register address translation does not occur for i 2 o shell interface accesses. register name: pci_ti2o_taddr register offset: 0x504 pci bits function pb bits 31-24 taddr 0-7 23-16 taddr 8-15 15-08 powerspan ii reserved 16-23 07-00 powerspan ii reserved 24-31 name type reset by reset state function taddr[15:0] r/w pri_rst 0 translation address (through substitution) when the ta_en bit in the ?pci i2o target image control register? on page 352 is set, taddr[15:0] replaces the pci bus upper address bits, up to the size of the image.
12. register descriptions 357 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.64 i2o control and status register register name: i2o_csr register offset: 0x508 pci bits function pb bits 31-24 powerspan ii reserved 0-7 23-16 powerspan ii reserved 8-15 15-08 powerspan ii reserved 16-23 07-00 hopl_size emtr ofl ipl xi 2 o_ en i 2 o_en 24-31 i name type reset by reset state function hopl_size [2:0] r/w pri_rst 0 host outbound post list size specifies the size of the host outbound post list circular fifo in the host memory. the iop must program this field when powerspan ii extended outbound option support is enable (see ta b l e 8 4 ). emtr r/w pri_rst 0 empty fifo read response the empty fifo read response bit determines the powerspan ii response to an iop read of the ?i2o inbound post list bottom pointer register? on page 365 or the ?i2o outbound free list bottom pointer register? on page 368 . if the emtr bit is set, a read from either of these registers when their corresponding fifo is empty will return 0xffff_ffff as read data to the iop. if the bit is not set, the contents of the corresponding pointer register will be returned as read data. 0 = return pointer on read when fifo empty 1 = return 0xffff_ffff on read when fifo empty ofl r pri_rst 0 outbound free list indicates status of the outbound free list fifo. if this bit is set, at least one outbound message frame is available in host memory. 0 = empty 1 = not empty
12. register descriptions 358 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com ipl r pri_rst 0 inbound post list indicates status of the inbound post list fifo. if this bit is set, there are inbound message frames for the iop to process. 0 = empty 1 = not empty xi 2 o_en r/w pri_rst 0 extended mfa enabled the iop programs this bit to enable the powerspan ii i 2 o extended capabilities support for the outbound option. the host outbound index offset register needs to be programmed with the offset in the pci i2o target image where the host outbound index register can be located for the outbound option support. this can be accomplished through the host outbound index alias register. the iop will need to program the following registers to support i 2 o extended capabilities: ? i2o iop outbound index register ? i2o host outbound index offset register ? i2o host outbound index alias register i 2 o_en r/w pri_rst 0 i 2 o enabled the local processor sets this bit to enable the powerspan ii i2o shell interface support. the iop must initialize the i2o inbound free list and post list fifo?s before enabling the powerspan ii i2o shell interface. when this bit is cleared, all ?pci-1 i2o target image base address register? on page 257 accesses on primary pci are retried. 0 = i2o disabled 1 = i2o enabled i name type reset by reset state function
12. register descriptions 359 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com hopl_size: this field specifies the size of the host outbound post list circular fifo in the host memory. the iop must program this field when powerspan ii extended outb ound option support is enabled. table 84: host outbound post list size hopl_size [2:0] max no. of mfas per fifo memory required per fifo (kbytes) powerspan ii iop host outbound index register bits incremented 000 001 256 1 iop_oi [9:2] 010 1k 4 iop_oi [11:2] 100 4k 16 iop_oi [13:2]
12. register descriptions 360 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.65 i2o queue base address register this register specifies the locatio n and size of the inbound and outbound queues in processor memory space. the iop must program this register before en abling the powerspan ii i2o shell interface. fifo_size: this field specifies the size of the circular fifos in the iop local memory. total fifo memory allocation is four times the single fifo size (see table 85 ). register name: i2o_queue_bs register offset: 0x50c pci bits function pb bits 31-24 pb_i2o_bs 0-7 23-16 pb_i2o_bs powerspan ii reserved 8-15 15-08 powerspan ii reserved 16-23 07-00 powerspan ii reserved fifo_size 24-31 i2o_queue_bs description name type reset by reset state function pb_i2o_bs [11:0] r/w pri_rst 0 processor bus i2o base address the pb_i2o_bs field specifies the base address of the 1 mb block of embedded powerpc memory that contains the four fifos (inbound free list, inbound post list, outbound free list, outbound post list). the four fifos are of equal size, but do not need to be in contiguous memory locations. the pb_i2o_bs field is aliased in the most significant 12 bits of each of the powerspan ii i2o bottom and top pointer registers. fifo_size [2:0] r/w pri_rst 0 fifo size this field specifies the size of the circular fifos in the iop local memory. total fifo memory allocation is four times the single fifo size (see table 85 ) table 85: i2o fifo sizes fifo_size [2:0] maximum number of mfas per fifo memory required per fifo (kbytes) powerspan ii i2o pointer bits incremented a 000 256 1 i2o_ptr [9:2] 001 1k 4 i2o_ptr [11:2] 010 4k 16 i2o_ptr [13:2]
12. register descriptions 361 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 011 16k 64 i2o_ptr [15:2] 100 64k 256 i2o_ptr [17:2] a. i2o_ptr is one of the following: ifl_bot, ifl_top, ip l_bot, ipl_top, ofl_bot, ofl_top, opl_bot, opl_top table 85: i2o fifo sizes fifo_size [2:0] maximum number of mfas per fifo memory required per fifo (kbytes) powerspan ii i2o pointer bits incremented a
12. register descriptions 362 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.66 i2o inbound free list bottom pointer register bot: this pointer gives the address offset for the in bound free list bottom pointer from pb_i2o_bs. this pointer is initialized by the iop and maintained by powerspan ii. this pointer is incremented by four for each pci read from the inbound queue. register name: ifl_bot register offset: 0x510 pci bits function pb bits 31-24 pb_i2o_bs 0-7 23-16 pb_i2o_bs bot 8-15 15-08 bot 16-23 07-00 bot 0 0 24-31 i name type reset by reset state function pb_i2o_bs [11:0] r pri_rst 0 processor bus i2o base address bot [17:0] r/w pri_rst 0 inbound free list bottom pointer this pointer gives the address offset for the inbound free list bottom pointer from pb_i2o_bs. if the initial values of the inbound free list bottom and top pointers are the same, the inbound free list is empty. the user can program the top pointer to be four less than the bottom pointer an d then write to the incr bit in the ?inbound free list top pointer increment register? on page 364 to make the inbound free list full.
12. register descriptions 363 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.67 i2o inbound free list top pointer register top: this pointer gives the address offset for the inbound free list top pointer from pb_i2o_bs. this pointer is initialized by the iop and can be incremented by four by writing a 1 to the incr bit in the ?inbound free list top pointer increment register? on page 364 . register name: ifl_top register offset: 0x514 pci bits function pb bits 31-24 pb_i2o_bs 0-7 23-16 pb_i2o_bs top 8-15 15-08 top 16-23 07-00 top 0 0 24-31 name type reset by reset state function pb_i2o_bs [11:0] r pri_rst 0 processor bus i2o base address top [17:0] r/w pri_rst 0 inbound free list top pointer this pointer gives the address offset for the inbound free list top pointer from pb_i2o_bs. if the initial values of the inbound free list bottom and top pointers are the same, the inbound free list is empty. the user can program the top pointer to be four less than the bottom pointer and then set the incr bit in the ?inbound free list top pointer increment register? on page 364 register to make the inbound free list full.
12. register descriptions 364 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.68 inbound free list top pointer increment register register name: ifl_top_inc register offset: 0x518 pci bits function pb bits 31-24 powerspan ii reserved 0-7 23-16 powerspan ii reserved 8-15 15-08 powerspan ii reserved 16-23 07-00 powerspan ii reserved incr 24-31 i name type reset by reset state function incr write 1 to set pri_rst 0 inbound free list top pointer increment write 1 to increment the pointer by four.
12. register descriptions 365 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.69 i2o inbound post list bottom pointer register bot: this pointer gives the address offset for the in bound post list bottom pointer from pb_i2o_bs. this pointer is initialized by the iop and can be incremented by four by setting the incr bit in the ?i2o inbound post list bottom po inter increment register? on page 366 . register name: ipl_bot register offset: 0x51c pci bits function pb bits 31-24 pb_i2o_bs 0-7 23-16 pb_i2o_bs bot 8-15 15-08 bot 16-23 07-00 bot 0 0 24-31 name type reset by reset state function pb_i2o_bs [11:0] r pri_rst 0 processor bus i2o base address bot [17:0] r/w pri_rst 0 inbound post list bottom pointer this pointer gives the address offset for the inbound post list bottom pointer from pb_i2o_bs. the initial values of the inbound post list bottom and top pointers must be the same. after these pointers are initialized, the inbound post list is empty.
12. register descriptions 366 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.70 i2o inbound post list bott om pointer increment register register name: ipl_bot_inc register offset: 0x520 pci bits function pb bits 31-24 powerspan ii reserved 0-7 23-16 powerspan ii reserved 8-15 15-08 powerspan ii reserved 16-23 07-00 powerspan ii reserved incr 24-31 name type reset by reset state function incr write 1 to set pri_rst 0 inbound post list bottom pointer increment write 1 to increment the pointer by four.
12. register descriptions 367 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.71 i2o inbound post list top pointer register top: this pointer gives the address offset for the inbound post list top pointer from pb_i2o_bs. this pointer is initialized by the iop and maintained by powerspan ii. this poi nter is incremented by four for each pci write to the inbound queue. register name: ipl_top register offset: 0x524 pci bits function pb bits 31-24 pb_i2o_bs 0-7 23-16 pb_i2o_bs top 8-15 15-08 top 16-23 07-00 top 0 0 24-31 name type reset by reset state function pb_i2o_bs [11:0] r pri_rst 0 processor bus i2o base address top [17:0] r/w pri_rst 0 inbound post list top pointer this pointer gives the address offset for the inbound post list top pointer from pb_i2o_bs. the initial values of the inbound post li st bottom and top pointers should be the same. after these pointers are initialized, the inbound post list is empty.
12. register descriptions 368 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.72 i2o outbound free list bottom pointer register bot: this pointer gives the address offset for the outbound free list bottom pointer from pb_i2o_bs. this pointer is initialized by the iop an d can be incremented by four by writing a 1 to the incr bit in the ofl_bot_inc register. register name: ofl_bot register offset: 0x528 pci bits function pb bits 31-24 pb_i2o_bs 0-7 23-16 pb_i2o_bs bot 8-15 15-08 bot 16-23 07-00 bot 0 0 24-31 name type reset by reset state function pb_i2o_bs [11:0] r pri_rst 0 processor bus i2o base address bot [17:0] r/w pri_rst 0 outbound free list bottom pointer this pointer gives the address offset for the outbound free list bottom pointer from pb_i2o_bs. the initial values of the outbound free list bottom and top pointers must be the same. after these pointers are initialized, the outbound free list is empty.
12. register descriptions 369 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.73 i2o outbound free list bo ttom pointer increment register register name: ofl_bot_inc register offset: 0x52c pci bits function pb bits 31-24 powerspan ii reserved 0-7 23-16 powerspan ii reserved 8-15 15-08 powerspan ii reserved 16-23 07-00 powerspan ii reserved incr 24-31 name type reset by reset state function incr write 1 to set pri_rst 0 outbound free list bottom pointer increment write 1 to increment the pointer by four.
12. register descriptions 370 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.74 i2o outbound free li st top pointer register top: this pointer gives the address offset for the outbound free list top pointer from pb_i2o_bs. this pointer is initialized by the iop and maintained by powerspan ii. this pointer is incremented by four for each pci write to the outbound queue. register name: ofl_top register offset: 0x530 pci bits function pb bits 31-24 pb_i2o_bs 0-7 23-16 pb_i2o_bs top 8-15 15-08 top 16-23 07-00 top 0 0 24-31 name type reset by reset state function pb_i2o_bs [11:0] r pri_rst 0 processor bus i2o base address top [17:0] r/w pri_rst 0 outbound free list top pointer this pointer gives the address offset for the outbound free list top pointer from pb_i2o_bs. the initial values of the outbound free list bottom and top pointers must be the same. after these pointers are initialized, the outbound free list is empty.
12. register descriptions 371 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.75 i2o outbound post list bottom pointer register bot: this pointer gives the address offset for the outbound post list bottom pointer from pb_i2o_bs. this pointer is initialized by the iop and maintained by powerspan ii. this pointer is incremented by four for each pci read from the outbound queue. register name: opl_bot register offset: 0x534 pci bits function pb bits 31-24 pb_i2o_bs 0-7 23-16 pb_i2o_bs bot 8-15 15-08 bot 16-23 07-00 bot 0 0 24-31 name type reset by reset state function pb_i2o_bs [11:0] r pri_rst 0 processor bus i2o base address bot [17:0] r/w pri_rst 0 outbound post list bottom pointer this pointer gives the address offset for the outbound post list bottom pointer from pb_i2o_bs. the initial values of the outbound post list bottom and top pointers must be the same. after these pointers are initialized, the outbound post list is empty.
12. register descriptions 372 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.76 i2o outbound post li st top pointer register top: this pointer gives the address offset for the ou tbound post list top pointer from pb_i2o_bs. this pointer is initialized by the iop and can be incremented by four by writing 1 to the incr bit in the opl_top_inc register. register name: opl_top register offset: 0x538 pci bits function pb bits 31-24 pb_i2o_bs 0-7 23-16 pb_i2o_bs top 8-15 15-08 top 16-23 07-00 top 0 0 24-31 name type reset by reset state function pb_i2o_bs [11:0] r pri_rst 0 processor bus i2o base address top [17:0] r/w pri_rst 0 outbound post list top pointer this pointer gives the address offset for the outbound post list top pointer from pb_i2o_bs. the initial values of the outbound post list bottom and top pointers must be the same. after these pointers are initialized, the outbound post list is empty.
12. register descriptions 373 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.77 i2o outbound post list top pointer increment register register name: opl_top_inc register offset: 0x53c pci bits function pb bits 31-24 powerspan ii reserved 0-7 23-16 powerspan ii reserved 8-15 15-08 powerspan ii reserved 16-23 07-00 powerspan ii reserved incr 24-31 name type reset by reset state function incr write 1 to set pri_rst 0 outbound post list top pointer increment write 1 to increment the pointer by four.
12. register descriptions 374 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.78 i2o host outbound index offset register oio[9:0]: specifies the i2o target image offset wher e the i2o host outbound index register is located within the powerspan ii i2o target image. the i2o host outbound index register must be in the first 4 kbytes of the powerspan ii i2o targ et image and be aligned to a 4-byte boundary. register name: host_oio register offset: 0x540 pci bits function pb bits 31-24 powerspan ii reserved 0-7 23-16 powerspan ii reserved 8-15 15-08 powerspan ii reserved oio 16-23 07-00 oio 0 0 24-31 name type reset by reset state function oio[9:0] r/w pri_rst 0 host outbound index offset specifies the i2o target image offset where the i2o host outbound index register is located within the powerspan ii i2o target image. this register must not be programmed with the following values: 0x030, 0x034, 0x040, 0x044.
12. register descriptions 375 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.79 i2o host outboun d index alias register this register is requi red for powerspan ii i ? o outbound option support. this is an alias to the i2o host outbound index register in th e powerspan ii i2o target image. th e host maintains this register. this register indicates the address in host memory from which the host is to retrieve the next outbound xmfa. this regist er is initialized by the iop with an index received from th e host in an i2o message. the register will be written by the host during i2o outbound option message passing. if the i2o host outbound index register and the i2 o iop outbound index register differ, then the outbound post list interrupt status bit is set in the opl_is register at offset 0x30 of the pci i2o target image. when these registers cont ain the same host memory address, the interrupt is cleared. this feature is only supported when the i2o outbound option is enabled with xi2o_en bit in the ?i2o control and status register? on page 357 . the hopl_size field in the ?i2o control and status register? on page 357 determines the alignment of this index register. register name: host_oia register offset: 0x544 pci bits function pb bits 31-24 oia 0-7 23-16 oia 8-15 15-08 oia 16-23 07-00 oia 0 0 24-31 name type reset by reset state function oia[29:0] r/w pri_rst 0 host outbound index alias register
12. register descriptions 376 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.80 i2o iop out bound index register this register is required for powe rspan ii i2o outbound option suppor t. this register indicates the address in host memory to which the iop is to po st the next outbound xmfa. the iop maintains this register. if the i2o host outbound index register and the i2 o iop outbound index register differ, then the outbound post list interrupt status bit is set in the opl_is register at offset 0x30 of the pci i2o target image. when these registers cont ain the same host memory addr ess, the interrupt is cleared. this feature is only supported when the i2o outbound option is enabled with the xi2o_en bit in the ?i2o control and status register? on page 357 . the hopl_size bit in the ?i2o control and status register? on page 357 determines the alignment of this index register. register name: iop_oi register offset: 0x548 pci bits function pb bits 31-24 oi 0-7 23-16 oi 8-15 15-08 oi 16-23 07-00 oi 0 0 24-31 i name type reset by reset state function oi[29:0] r/w pri_rst 0 iop outbound index
12. register descriptions 377 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.81 i2o iop outbound index increment register the iop writes 1 to incr to increm ent the iop outbound index register. register name: iop_oi_inc register offset: 0x54c pci bits function pb bits 31-24 powerspan ii reserved 0-7 23-16 powerspan ii reserved 8-15 15-08 powerspan ii reserved 16-23 07-00 powerspan ii reserved incr 24-31 i name type reset by reset state function incr write 1 to set pri_rst 0 iop outbound index increment write 1 to increment the pointer by four.
12. register descriptions 378 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.82 pci-2 configuration registers register offset: 0x800-0x8fc pci-2 configuration function the pci-2 configuration registers are func tionally identical to the pci-1 configurat ion registers from offsets 0x000-0fc. documentation of the pci-2 configuration space is the same as the pci-1 interface, shifting the register offsets up by 0x800 and swapping pci-1 and pci-2 everywhere.
12. register descriptions 379 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 12.5.83 pci-2 target image c ontrol and status registers register offset: 0x900-0x9fc pci-2 target image function the pci-2 target image control and status registers are functi onally identical to the pci-1 target image control and status registers from offsets 0x100-1fc. documentation of the pci-2 target images is the same as the pci-1 images, shifting the register offsets up by 0x800 and swap ping pci-1 and pci-2 everywhere.
12. register descriptions 380 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com
381 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 13. electrical and signal characteristics this chapter describes the electrical characteristics of the powerspan ii device. it also details the pin-outs of both the single pci powerspan ii and dual pci powerspan ii. the following topics are discussed: ? ?electrical characteristics? on page 381 ? ?power dissipation? on page 383 ? ?operating conditions? on page 384 13.1 electrical characteristics powerspan ii?s electrical characteristics are defi ned by pci electrical char acteristics and non-pci electrical char acteristics. 13.1.1 pci electrical characteristics powerspan ii's pci interfaces are electrically compatible with th e 3.3v and the 5.0v signaling interfaces as defined by the pci 2.2 specification . powerspan ii supports the compactpci hot swap specification revision 2.0 and is classified as hot swap silicon. powerspan ii is compliant with the pci local bus specification revision 2.2 regarding device accessibility after release of local_pci_rst_ through initially retrying. optionally devices can choose to initially no t respond after release. 13.1.2 non-pci electri cal characteristics the following table, table 86 , specifies the required dc characteristics of all non-pci powerspan ii signal pins. table 86: hbga electrical characteristics (non-pci) a symbol parameter condition min max units v il input low voltage v out ? v oh (min) or v out ? v ol (max) - 0.3 0.8 v v ih input high voltage (5 v tolerant lvttl) 2.0 v dd + 0.3 v iin input leakage current v in = 0 v or v in = v dd 5a iin input leakage current (internal pull-up) v in = 0 v or v in = v dd -2.0 -100 a
13. electrical and signal characteristics 382 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com iin input leakage current (internal pull-down) v in = 0 v or v in = v dd 2.0 100 a v oh output high voltage v dd = min, i oh = -10ma 2.4 v v ol output low voltage v dd = min, i oh = 10ma 0.4 v c in input capacitance 10 pf i ol b output low current (65 ohm output) v ol =1.5v 25 100 ma a. non-pci dc electrical characteristics (ta= -40 c to 85 c ) b. compactpci hot swap led pin table 86: hbga electrical characteristics (non-pci) a symbol parameter condition min max units
13. electrical and signal characteristics 383 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 13.2 power dissipation table 87 shows the single pci powerspan ii power dissipation.. table 88 shows the dual pci powe rspan ii power dissipation table 87: single pci powerspan ii power dissipation processor bus clock pci-1 clock vdd i/o vdd core maximum 50 mhz 33 mhz 0.17 0.93 1.1 w 66 mhz 33 mhz 0.2 1.1 1.3 w 100 mhz 66 mhz 0.4 1.9 2.3 w table 88: dual pci powerspan ii power dissipation processor bus clock pci-1 clock pci-2 clock vdd i/o vdd core maximum 50 mhz 33 mhz 25 mhz 0.17 0.93 1.1 w 66 mhz 33 mhz 33 mhz 0.2 1.1 1.3 w 100 mhz 66 mhz 66 mhz 0.4 1.9 2.3 w
13. electrical and signal characteristics 384 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 13.3 operating conditions 13.3.1 recommended operating conditions the following table, table 89 , specifies the recommended operat ing conditions of the powerspan ii. 13.3.2 handling and st orage specifications after encapsulation, cure cavity dow n assemblies are jesd22-a112 moisture sensitivity category 3. from that point on, parts are to be handled to the following criteria: 1. from encapsulation cure to bga/pga attach, class 3 modules can be exposed for a maximum cumulative time of eight days to an environment of no more than 30 oc and/or 60% rh. if this condition is exceeded, modules are to be baked at 125 o c +/- 10 oc for 24 hours minimum or at other qualified bake parameters. 2. modules shall be placed in an esd carrier. each mo dule shall be orientated in the same way. when preparing for shipment to stock location, modules are to be baked at 125 o c +/- 10 o c for 24 hours minimum or at other qualified bake parameters . modules are to be sealed within 24 hours for class 3 modules in a moisture barrier esd bag with desiccant. this bakeout procedure can be repeated once to remain in compliance. 3. failure to comply with this requirement can result in die to die pad, encapsulant to soldermask or encapsulant to die delami nation during reflow. table 89: operating and storage conditions symbol parameter min max units vdd i/o i/o dc supply voltage 3.15 3.45 v vdd core core supply voltage 2.38 2.63 v px_vdda pll supply voltage 2.38 2.63 v ta a m b i e n t temperature -40 +85 c h humidity 0 80 % relative humidity
13. electrical and signal characteristics 385 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 13.3.3 absolute maximum ratings the following table, table 90 , specifies the absolute maximum ratings of powerspan ii. table 90: absolute maximum ratings symbol parameter limits units vdd core a b a. functional operation at the maximums is not guaranteed. stress beyond those listed can affect device reliability or cause permanent damage to powerspan ii. b. vdd core/ px_vdda must not exceed vdd i/o by more than 0.4 v. this includes during power-on reset. c. vdd i/o must not exceed vdd core/ px_vdda by more than 1.6 v. this includes during power-on reset. d. these limits only apply to overshoot and undershoot. cell functionality is not implied. e. vin must not exceed vdd i/o by more than 2.5 v at any time. this includes during power-on reset. core supply voltage -0.3 to 2.7 v vdd i/o a c i/o supply voltage -0.3 to 3.6 v px_vdda a b pll supply voltage -0.3 to 2.7 v vin a d e dc input voltage (lvttl) -0.3 to vdd + 0.3 v vin a d e dc input voltage (5 v tolerant lvttl) -0.6 to 5.5 v tstg storage temperature -65 to 150 c
13. electrical and signal characteristics 386 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com
387 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 14. package information this appendix discusses powerspan ii?s packaging (mechanical) features. th e following topics are discussed: ? ?package characteristics? on page 387 ? ?thermal characteri stics? on page 391 14.1 package characteristics powerspan ii?s package characteristics are summarized in the following sections. 14.1.1 single pci powe rspan ii 420 hsbga figure 28 illustrates the top, side, and bott om views of the powerspan ii package. table 91: package characteristics feature description package type 420 hsbga package body size 35mm jedec specification jedec mo-151 variation bat-1
14. package information 388 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 28: 420 hsbga 14.1.1.1 package notes 1. all dimensions in mm 2. all dimensions and tolerance conform to ansi y14.5m - 1994 3. conforms to jedec ms-034 variation bar-1 notes: 1. all dimensions in mm. 2. all dimension and tolerances conform to ansi y14.5m-1994. 3. conforms to jedec mo-034 variation bar-1.
14. package information 389 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 14.1.2 dual pci powerspan ii 480 hsbga figure 29 illustrates the top, side, and bott om views of the powerspan ii package. table 92: package characteristics feature description package type 480 hsbga package body size 37.5mm jedec specification jedec mo-151 variation bat-1
14. package information 390 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 29: 480 hsbga 14.1.2.1 package notes 1. all dimensions in mm 2. all dimensions and tolerance conform to ansi y14.5m - 1994 3. conforms to jedec mo-151 variation bat-1 notes: 1. all dimensions in mm. 2. all dimension and tolerances conform to ansi y14.5m-1994. 3. conforms to jedec mo-151 variation bat-1.
14. package information 391 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 14.2 thermal characteristics the thermal performance of powerspan ii package is represented by the following parameters: 1. ? ja , thermal resistance from junction to ambient ? ja = (t j - t a ) / p where, t j is the junction temperature t a is the ambient temperature p is the power dissipation ? ja represents the resistance to the heat flows from th e chip to ambient air. it is an index of heat dissipation capability. lower ? ja means better thermal performance. 2. ? jt , thermal characterization parame ter from junction-to-top center ? jt = (t j - t t ) / p where t t is the temperature of the top-center of the package ? jt is used to estimate junction temperature by measuring t t in actual environment. 3. 3. ? jc , thermal resistance from junction to case ? jc = (t j ? t c ) / p where, t c is the case temperature ? jc is a measure of package internal thermal resistance from chip to package exterior. the value is dependent upon pa ckage material and package geometry. ? ja, ? jc and ? jt simulation are carried out to show the thermal performance of the powerspan ii.
14. package information 392 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 14.2.1 single pci 420 hsbga package the thermal characteristics for the 420 package are based on the parameters in table 93 . table 94 shows the thermal characterization parameters from junction-to-top center ( ? jt ) and the thermal resistance from junction to case for the 420 package. these values are based on the parameters described in table 93 . table 93: thermal parameters package conditions package type hsbga 420 package size 35 x 35 x 2.33 mm 3 pitch 1.27 mm pad size 318 x 318 mil 2 chip size 232 x 232 mil 2 substrate (layers) 4 layer substrate thickness 0.56 mm pcb conditions (jedec jesd51-7) pcb layers 4 layer pcb dimensions 101.6 x 114.3 mm pcb thickness 1.6 mm simulation conditions power dissipation 3.0 watts ambient temperature 55 ? c table 94: 420 hsbga package performance theta ja (c/w) psi jt (c/w) theta jc (c/w) 0 m/s 1 m/s 2 m/s 16.5 14.6 13.2 5.48 6.80
14. package information 393 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 14.2.2 dual pci 480 hsbga package the thermal characteristics for the 480 package are based on the parameters in table 95 . table 96 shows the thermal characterization parameters from junction-to-top center ( ? jt ) and the thermal resistance from junction to case for the 480 package. these values are based on the parameters described in table 95 . table 95: thermal parameters package conditions package type hsbga 480l package size 37.5 x 37.5 x 2.33 mm 3 pitch 1.27 mm pad size 303 x 303 mil 2 chip size 253 x 253 mil 2 substrate (layers) 4 layer substrate thickness 0.56 mm pcb conditions (jedec jesd51-7) pcb layers 4 layer pcb dimensions 101.6 x 114.3 mm pcb thickness 1.6 mm simulation conditions power dissipation 3.0 watts ambient temperature 85 ? c table 96: 480 pbga package performance theta ja (c/w) psi jt (c/w) theta jc (c/w) 0 m/s 1 m/s 2 m/s 15.1 13.2 11.8 4.87 6.00
14. package information 394 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com
395 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 15. ac timing this chapter describes powerspan ii?s ac timing parameters. the following topics are discussed: ? ?single pci powerspan ii ti ming parameters? on page 396 ? ?dual pci powerspan ii timing parameters? on page 402 ? ?timing diagrams? on page 408 15.1 overview this chapter describes the timing information for th e powerspan ii device. the timing for the both the single and the dual pci powerspan ii?s pro cessor bus interface is 100 mhz, while the pci interface(s) can operate either at 33 mhz or 66 mhz.
15. ac timing 396 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 15.2 single pci powerspan ii timing parameters the timing parameters specified in this document ar e guaranteed by design. test conditions for timing parameters in table 97 to table 101 are: ? commercial (c): 0oc to 70oc, 3.15 - 3.45v, 2.38 - 2.63v ? industrial (i): -40oc to 85 oc, 3.15 - 3.45v, 2.38 - 2.63v table 97: reset, and clock timing parameters timing parameter description ce/ie units note min max reset timing t 100 power-up reset pulse width 500 ns 1 t 101 back end power stable to back end power-up reset released. 500 ns t 102 clock frequency stable before release of power-up reset 0 ns 2 t 103 pll lock time 100 400 us 3 t 104 reset propagation delay 20 ns t 105 pci bus reset timing after the negation of po_rst_ 50 ns t 428 trst_ pulse width 500 ns 4 power-up option timing t 110 power-up option setup time on multiplexed system pins 10 ns t 111 power-up option hold time on multiplexed system pins 3.0 10 ns 5 int[4]_ 3.2 10 ns 5 t 112 power-up option setup time to pb_rstconf_ 10 ns t 113 power-up option hold time from pb_rstconf_ 5 ns t 114 pb_rstconf_ pulse width 1 pb_clks processor clock timing t 120 pb_clk period 10 40 ns pb_clk frequency 25 100 mhz t 121 pb_clk high time 4 ns t 122 pb_clk low time 4 ns t 123 pb_clk slew rate 2 v/ns
15. ac timing 397 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 1. pulse width measured from vdd core (2.5v), vdd i/o (3.3v), and px_vdda supplies in specification 2. required for pb_clk, and p1_clk. this parameter ensures th at each pll locks. if a frequency change is required, a new powe r-up sequence must be initiated. 3. this parameter is a function of the slowest frequency of pb_clk, and p1_clk. the minimum occurs at 100 mhz, the maximum at 25 mhz. after this time, powerspan ii is synchronized to external buses a nd able to participate in transa ctions once externally applied resets are released. 4. assertion of trst_ is required at power-up to initializ e the jtag controller and configure the boundary scan register for normal system oper- ation. 5. the maximum specification ensures correct power-up levels on pb_fast, and p1_m66en and ensures stable system levels on int [5:1]_ before the power-up reset sequence completes. the int[4]_ signal has a minimum time of 3.2. 6. the ratio of largest to smallest cloc k period for pb_clk, p1_clk must be strictly less than four. for example, if pb_clk p eriod is 12 ns, the period of p1_clk must be less than 48 ns. t 124 pb_clk cycle to cycle jitter 300 ps pci clock timing t 130 p1_clk period 15 40 ns p1_clk frequency 25 66 mhz t 131 p1_clk high time 6 ns t 132 p1_clk low time 6 ns t 133 p1_clk slew rate 2 v/ns t 134 p1_clk cycle to cycle jitter 300 ps clock to clock relationships t 140 clock period ratio 1 < 4 - 6 table 97: reset, and clock timing parameters timing parameter description ce/ie units note min max
15. ac timing 398 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com powerspan ii?s pci interf ace can be configured for operating frequencies between 25 and 33 mhz by ensuring that the pin px_m66en is connected to logic zero. table 98 summarizes the timing behavior of a powerspan ii pci interface configured in this wa y. this table is valid for operation in 3.3v or 5.0v signaling environments. 1. this group of point to point signals include: p1_req[1]#, p1_gnt[4:1]#, and pci_gnt[7:5]#. 2. this group of point to point signals include: p1_gnt[1]#, p1_req[4:1]#, and pci_req[7:5]#. 3. in the adapter scenario, an external agent controls both p1_req64# and p1_rst#. 4. in the pci local bus specific ation (revision 2.2) this value is requ ired to be 0 ns. 5. in the host scenario, powerspan ii controls both p1_req64# and p1_rst#. table 98: pci 33 mhz timing parameters timing parameter description ce/ie units note min max t 200 float to active delay 2 ns t 201 active to float delay 28 ns t 202 signal valid delay bussed signals 2 11 ns point to point signals 2 12 ns 1 t 203 input setup time bussed signals 7 ns point to point signals 10 ns 2 t 204 input hold time 0 ns t 205 p1_req64# to p1_rst# setup time adapter scenario 10 pb_clks 3 host scenario 10 pb_clks 5 t 206 p1_rst# to p1_req64# hold time adapter scenario 2.3 ns 3, 4 host scenario 0 50 ns 5 t 207 reset to float 40 ns
15. ac timing 399 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com each powerspan ii pci interface can be configured for 66 mhz operating freque ncies by ensuring that the pin px_m66en is co nnected to logic one. table 99 summarizes the timing behavior of a powerspan ii pci interface configured in this way. th is table is valid for oper ation in a 3v signaling environment. 1. this group of point to point signals in clude: p1_req[1]#, p1_gnt[4:1]#, and pci_gnt[7:5]#. 2. this group of point to point signals include: p1_gnt[1]#, p1_req[4:1]#, and pci_req[7:5]#. 3. in the adapter scenario, an external agent controls both p1_req64# and p1_rst#. 4. in the host scenario, powerspan ii controls both p1_req64# and p1_rst#. table 99: pci 66 mhz timing parameters timing parameter description ce/ie units note min max t 200 float to active delay 1 ns t 201 active to float delay 14 ns t 202 signal valid delay bussed signals 16.0ns point to point signals 1 6.0 ns 1 t 203 input setup time bussed signals 3.0 ns point to point signals 5.0 ns 2 t 204 input hold time 0 ns t 205 p1_req64# to p1_rst# setup time adapter scenario 10 pb_clks 3 host scenario 10 pb_clks 4 t 206 p1_rst# to p1_req64# hold time adapter scenario 2.3 ns 3 host scenario 0 50 ns 4 t 207 reset to float 40 ns
15. ac timing 400 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the powerspan ii pb interface can be configured for 100 mhz operating frequencies. table 100 summarizes the timing behavior of a powerspa n ii pb interface configured for 100 mhz. 1. numbers measured in to lumped 35 pf load. 2. the transaction parameter group of signals includes: pb_a[0:31], pb_ap[0:3], pb _tsiz[0:3], pb_tt[0:4], pb_tbst_, pb_gbl_, pb_ci_, pb_d[0:63], pb_dp[0:7]. 3. the transaction control group of signals includes: pb _ts_, pb_abb_, pb_dbb_, pb_ta_, pb_dva_l, pb_tea_, pb_aack_. 4. the transaction arbitration group outputs includes: pb_br[1]_, pb_bg[1:3]_, pb_dbg[1:3]_ 5. the point to point signals include: pb_bg[1]_, pb_br[1:3]_, pb_dbg[1]_ table 100: pb timing parameters timing parameter description ce/ie units note min max t 302 pb_clk to output valid delay parameter group outputs 1.0 5.0 ns 1,2 control group outputs 1.0 5.0 ns 1,3 pb_artry_ 1.0 5.0 ns 1 arbitration group outputs 1.0 5.0 ns 1, 4 t 303 input setup time bussed signals 3.0 ns pb_ap 2.0 ns point to point signals 3.0 ns 5 t 304 input hold time 0.3 ns
15. ac timing 401 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 1. numbers measured into 35 pf load. 2. powerspan ii synchronizes these inputs before using th em. this parameter must be me t for determinis tic response time. 3. powerspan ii filters these inputs to ensure spurious low going pu lses are not recognized as active interrupts. an interrup t pin is considered valid if three pb_clk samples yield the same result. table 101: miscellaneous timing parameters timing parameter description ce/ie units note min max interrupt timing t 400 float to active delay 2 15 ns 1 t 401 active to float delay 2 15 ns 1 t 402 input setup time 3 ns 2 t 403 input hold time 0.5 ns 2 t 404 pulse width 4 pb_clks 3 i 2 c timing t 410 i2c_sclk period 1024 1024 pb_clks t 411 i2c_sclk high time 512 512 pb_clks t 412 i2c_sclk low time 512 512 pb_clks t 413 stop condition setup time 512 512 pb_clks t 414 bus free time 512 pb_clks t 415 start condition setup time 1024 pb_clks t 416 start condition hold time 512 512 pb_clks t 417 data output valid time 256 256 pb_clks t 418 data output hold time 256 256 pb_clks t 419 data sample time 256 256 pb_clks
15. ac timing 402 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 15.3 dual pci powerspan ii timing parameters the timing parameters specified in this document ar e guaranteed by design. test conditions for timing parameters in table 102 to table 106 are: ? commercial (c): 0oc to 70oc, 3.15 - 3.45v, 2.38 - 2.63v ? industrial (i): -40oc to 85 oc, 3.15 - 3.45v, 2.38 - 2.63v table 102: reset, and clock timing parameters timing parameter description ce/ie units note min max reset timing t 100 power-up reset pulse width 500 ns 1 t 101 back end power stable to back end power-up reset released. 500 ns t 102 clock frequency stable before release of power-up reset 0 ns 2 t 103 pll lock time 100 400 us 3 t 104 reset propagation delay 20 ns t 105 pci bus reset timing after the negation of po_rst_ 50 ns t 428 trst_ pulse width 500 ns 4 power-up option timing t 110 power-up option setup time on multiplexed system pins 10 ns t 111 power-up option hold time on multiplexed system pins 3.0 10 ns 5 t 112 power-up option setup time to pb_rstconf_ 10 ns t 113 power-up option hold time from pb_rstconf_ 5 ns t 114 pb_rstconf_ pulse width 1 pb_clks processor clock timing t 120 pb_clk period 10 40 ns pb_clk frequency 25 100 mhz t 121 pb_clk high time 4 ns t 122 pb_clk low time 4 ns t 123 pb_clk slew rate 2 v/ns t 124 pb_clk cycle to cycle jitter 300 ps
15. ac timing 403 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 1. pulse width measured from vdd core (2.5v), vdd i/o (3.3v), and px_vdda supplies in specification 2. required for pb_clk, p1_c lk and p2_clk. this parameter ensures that each pl l locks. if a frequency ch ange is required, a n ew power-up sequence must be initiated. 3. this parameter is a function of the slowest frequency of pb _clk, p1_clk, and p2_clk. the mini mum occurs at 100 mhz, the ma ximum at 25 mhz. after this time, powerspan ii is synchr onized to external buses and able to par ticipate in transactio ns once externally ap plied resets are released. 4. assertion of trst_ is required at power-up to initializ e the jtag controller and configure the boundary scan register for normal system oper- ation. 5. the maximum specification ensures correct power-up levels on pb_fast, p1_m66en and p2_m66en and ensures stable system leve ls on int[5:1]_ before the power-up reset sequence completes. 6. the ratio of largest to sm allest clock period for pb_clk, p 1_clk, p2_clk must be strictly less than four. for example, if pb_clk period is 12 ns, the periods of p1_clk and p2_c lk must be each less than 48 ns. pci clock timing t 130 p1_clk, p2_clk period 15 40 ns p1_clk, p2_clk frequency 25 66 mhz t 131 p1_clk, p2_clk high time 6 ns t 132 p1_clk, p2_clk low time 6 ns t 133 p1_clk, p2_clk slew rate 2 v/ns t 134 p1_clk, p2_clk cycle to cycle jitter 300 ps clock to clock relationships t 140 clock period ratio 1 < 4 - 6 table 102: reset, and clock timing parameters timing parameter description ce/ie units note min max
15. ac timing 404 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com powerspan ii?s pci interf ace can be configured for operating frequencies between 25 and 33 mhz by ensuring that the pin px_m66en is connected to logic zero. table 103 summarizes the timing behavior of a powerspan ii pci interface configured in this wa y. this table is valid for operation in 3.3v or 5.0v signaling environments. 1. this group of point to point signals include: p1_req[1 ]#, p2_req[1]#, p1_gnt[4:1]#, p2_gnt[4:1]#, and pci_gnt[7:5]#. 2. this group of point to point signals include: p1_gnt[1]#, p2_gnt[1]#, p1_req[4:1]#, p2_req[4:1]#, and pci_req[7:5]#. 3. in the adapter scenario, an external agent controls both p1_req64# and p1_rst#. 4. in the host scenario, powerspan ii controls both p1_req64# and p1_rst#. table 103: pci 33 mh z timing parameters timing parameter description ce/ie units note min max t 200 float to active delay 2 ns t 201 active to float delay 28 ns t 202 signal valid delay bussed signals 2 11 ns point to point signals 2 12 ns 1 t 203 input setup time bussed signals 7 ns point to point signals 10 ns 2 t 204 input hold time 0 ns t 205 p1_req64# to p1_rst# setup time adapter scenario 10 pb_clks 3 host scenario 10 pb_clks 4 t 206 p1_rst# to p1_req64# hold time adapter scenario 2.3 ns 3 host scenario 0 50 ns 4 t 207 reset to float 40 ns
15. ac timing 405 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com each powerspan ii pci interface can be configured for 66 mhz operating freque ncies by ensuring that the pin px_m66en is co nnected to logic one. table 104 summarizes the timi ng behavior of a powerspan ii pci interface configured in this way. th is table is valid for oper ation in a 3v signaling environment. 1. this group of point to point signals include: p1_req[1]#, p2_req[1]#, p1_gnt[4:1]#, p2_gnt[4:1]#, and pci_gnt[7:5]#. 2. this group of point to point signals include: p1_gnt[1]#, p2_gnt[1]#, p1_req[4:1]#, p2_req[4:1]#, and pci_req[7:5]#. 3. in the adapter scenario, an external agent controls both p1_req64# and p1_rst#. 4. in the host scenario, powerspan ii controls both p1_req64# and p1_rst#. table 104: pci 66 mh z timing parameters timing parameter description ce/ie units note min max t 200 float to active delay 1 ns t 201 active to float delay 14 ns t 202 signal valid delay bussed signals 16.0ns point to point signals 1 6.0 ns 1 t 203 input setup time bussed signals 3.0 ns point to point signals 5 ns 2 t 204 input hold time 0 ns t 205 p1_req64# to p1_rst# setup time adapter scenario 10 pb_clks 3 host scenario 10 pb_clks 4 t 206 p1_rst# to p1_req64# hold time adapter scenario 2.3 ns 3 host scenario 0 50 ns 4 t 207 reset to float 40 ns
15. ac timing 406 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the powerspan ii pb interface can be configured for 100 mhz operating frequencies. table 105 summarizes the timing behavior of a powerspa n ii pb interface configured for 100 mhz. 1. numbers measured in to lumped 35 pf load. 2. the transaction parameter group of signals includes: pb_a[0:31], pb_ap[0:3], pb _tsiz[0:3], pb_tt[0:4], pb_tbst_, pb_gbl_, pb_ci_, pb_d[0:63], pb_dp[0:7]. 3. the transaction control group of signals includes: pb _ts_, pb_abb_, pb_dbb_, pb_ta_, pb_dva_l, pb_tea_, pb_aack_. 4. the transaction arbitration group outputs includes: pb_br[1]_, pb_bg[1:3]_, pb_dbg[1:3]_ 5. the point to point signals include: pb_br[1:3]_ table 105: pb timing parameters timing parameter description ce/ie units note min max t 302 pb_clk to output valid delay parameter group outputs 1.0 5.0 ns 1,2 control group outputs 1.0 5.0 ns 1,3 pb_artry_ 1.0 5.0 ns 1 arbitration group outputs 1.0 5.0 ns 1, 4 t 303 input setup time bussed signals 3.0 ns pb_ap 2.0 ns point to point signals 3.0 ns 5 pb_bg[1]_ 3.8 ns pb_dbg[1]_ 3.2 ns pb_artry_ 3.2 ns t 304 input hold time pb_dbg[1]_ 0.2 ns all other inputs 0.3 ns
15. ac timing 407 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 1. numbers measured into 35 pf load. 2. powerspan ii synchronizes these inputs before using th em. this parameter must be me t for determinis tic response time. 3. powerspan ii filters these inputs to ensure spurious low going pu lses are not recognized as active interrupts. an interrup t pin is considered valid if three pb_clk samples yield the same result. table 106: miscellaneous timing parameters timing parameter description ce/ie units note min max interrupt timing t 400 float to active delay 2 15 ns 1 t 401 active to float delay 2 15 ns 1 t 402 input setup time 3 ns 2 t 403 input hold time 0.5 ns 2 t 404 pulse width 4 pb_clks 3 i 2 c timing t 410 i2c_sclk period 1024 1024 pb_clks t 411 i2c_sclk high time 512 512 pb_clks t 412 i2c_sclk low time 512 512 pb_clks t 413 stop condition setup time 512 512 pb_clks t 414 bus free time 512 pb_clks t 415 start condition setup time 1024 pb_clks t 416 start condition hold time 512 512 pb_clks t 417 data output valid time 256 256 pb_clks t 418 data output hold time 256 256 pb_clks t 419 data sample time 256 256 pb_clks
15. ac timing 408 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 15.4 timing diagrams the timing diagrams in this section apply to both the single pci powerspan ii and the dual pci powerspan ii. figure 30: power-up reset: compactpci adapter scenario notes: 1. p1_rst# configured as input 2. pb_rst_ and p2_rst# configured as output 3. if jtag is not used, the trst_ signal can be pulled low through a resistor (~2.5 kohm). reset ready for initialization t104 t104 t104 t104 t103 t428 t428 t102 t100 t100 t101 t100 t100 healthy_ po_rst_ trst_ px_clk plls locked p1_rst_dir p1_rst# pb_rst_dir pb_rst_ p2_rst_dir p2_rst# t105
15. ac timing 409 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 31: power-up options: multiplexed system pin approach figure 32: power-up options: configuration slave mode notes: 1. the power-up options latched by the configuration slave mode ta ke precedence over those latched by the multiplexed sy stem pins mode. 2. the configuration master runs configuration cycles as part of each hreset_ sequence. system level power-up level system level power-up level system level power-up level power-up level system level t111 t110 t101 healthy_ po_rst_ pb_fast p1_m66en p2_m66en int [5:1]_ configuration word t113 t112 t114 t114 pb_d[0:31] pb_rst_ pb_rstconf_
15. ac timing 410 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 33: clocking figure 34: pci timing t132 t130 t132 t131 t131 t130 t132 t130 t132 t131 t131 t130 t122 t120 t122 t121 t121 t120 pb_clk p1_clk p2_clk t201 t202 t200 t204 t203 pci clock (p1_clk, p2_clk) pci input pci output
15. ac timing 411 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 35: pci miscellaneous timing; compact pci adapter scenario figure 36: p1_req64_ assertion timing notes: 1. assertion of p1_req64# is determined by a power-up option. the c onfiguration slave mode power-up option is depicted in figure 32 on page 409 . 2. in a compactpci host applic ation, powerspan ii controls p1_rst# and p1_req64# and can ensure compliance with t205 and t206. in comp actpci adapter applicatio n, the system must guarantee p1_rst# negated after powe rspan ii power-up options loaded. t207 t206 t205 pci reset (p1_ rst#, p2_rst#) pci outputs p1_rst# p1_req64# configuration word t104 t104 t206 t205 pb_rst pb_rstconf pb_d[0:31] p1_req64# p1_rst#
15. ac timing 412 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 37: processor bus timing notes: 1. the transaction parameter group of signals in cludes: pb_a[0:31], pb_ap[0:3], pb_tsiz[0:3], pb_tt[0:4], pb_tbst_, pb_gbl_, pb_ci_, pb_d[0:63], pb_dp[0:7]. 2. the transaction control gro up of signals includes: pb_ts_, pb_abb_, pb_dbb_, pb_ta_, pb_dval_, pb_tea-, pb_aack_. 3. the transaction arbitration group outputs incl udes: pb_br[1]_, pb_bg[ 1:3]_, pb_dbg[1:3]_. t302 t302 t302 t302 t302 t302 t304 t303 pb_clk pb input pb parameter group outputs pb arbitration group outputs pb control group outputs pb_artry_
15. ac timing 413 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 38: interrupt timing figure 39: i 2 c timing t401 t400 t404 t403 t404 t402 pb_clk p1_inta#, p2_inta#, int [5:0] (output) p1_inta#, p2_inta#, int [5:0] (input) stop/start t419 t415 t414 t413 t418 t417 t416 t410 t412 t411 i2c_sclk i2c_sda
15. ac timing 414 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com
415 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 16. ordering information this appendix discusses powerspan ii?s ordering information. 16.1 ordering information when ordering the powerspan ii please refer to the device by its full part number, as displayed in table 107 . table 107: standard ordering information part number description frequency voltage (io/ core) temperature package diameter (mm) ca91l8200b- 100ce dual pci powerspan ii 100mhz 3.3/2.5 0 to 70c 480 hsbga 37.5 x 37.5 x 1.27 ca91l8200b- 100ie dual pci powerspan ii 100mhz 3.3/2.5 -40 to 85c 480 hsbga 37.5 x 37.5 x 1.27 ca91l8260b- 100ce single pci powerspan ii 100mhz 3.3/2.5 0 to 70c 420 hsbga 35 x 35 x 1.27 ca91l8260b- 100ie single pci powerspan ii 100mhz 3.3/2.5 -40 to 85c 420 hsbga 35 x 35 x 1.27
16. ordering information 416 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com
417 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com a. hardware implementation this chapter describe s hardware implementation issues that can be faced when using the powerspan ii device. the following topics are discussed: ? ?recommended bootstrap diode? on page 417 ? ?pll external decoupling? on page 418 a.1 overview when powerspan ii is designed into a system, certai n hardware implementation requirements must be addressed. this chapter deals with de sign issues in a powerspan ii system. a.2 recommended bootstrap diode idt recommends the use of a bootstrap diode betwee n the power rails. the bo otstrap diodes that are used in the system must be config ured so that a nominal core supp ly voltage (vdd core) is sourced from the i/o supply voltage (vdd i/o) until the power supply is active. in figure 40 , two schottky barrier diodes are connected in series. each of the diod es has a forward voltage (v f ) of 0.6v at high currents which provides a 1.2v current drop. this drop maintains 2.1v on the 2.5v power line. once the core/pll power supply stabiliz es at 2.5v, the bootst rap diode(s) are reverse biased with small leakage current. figure 40: bootstrap diodes for power-up sequencing the forward voltage must be effective at the current levels required by powerspan ii (< 1 amp). do not use diodes with only a nominal v f which drops to low at high current. i/o power core/pll power 3.3 v (vdd i/o) 2.5 v (vdd core/px_vdda)
a. hardware implementation 418 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com a.3 pll external decoupling the plls in the powerspa n ii device should be externally deco upled in order to have the cleanest possible supply environment. id t recommends two decoupling scen arios for powerspan ii. the first recommendation is a backwards co mpatible design that enables migrating powerspan ii users to employ the decoupling scheme used in the original powerspan ii. the second recommendation is for new powerspan ii designs. a.3.1 backwards compatible pll deco upling for migrating powerspan ii designs vdda is the voltage supply pin to the analog circuits in the p ll. noise on vdda can cause phase jitter at the output of the pll. to provide isolation from the noisy internal digital circuitry, a filter circuit can be pl aced on vdda (see figure 41 ). figure 41: pll power filter all wire lengths must be ke pt short in order to minimize coupling from other signals. a.3.1.1 recommended decoupling capacitors powerspan ii requires the core supply voltage (vdd core (2.5v)) and i/o supply voltage (vdd i/o (3.3v)) be decoupled to reduce switching noise. on e bulk capacitor of 10 uf is recommended for the vdd core and vdd i/o supplies. every third pair of power and ground pins must be decoupled with a 0.1 uf surface mount capacitor to redu ce high frequency switching noise. the track lengths from the power and ground pins to the capacitors must be kept as short. based on this recommendation, eight 0.1uf capacitors are required for the i/o supply and twelve 0.1uf capacitors for the core supply. in order to keep the track lengths to the capacitors as short as possible, use integrated capacitor components. it is possible to obtain components which have four 0.1uf capacitors in a 0612 size package. other quantities and va lues of capacitors can be used at the discretion of the designer. vdd vdda c = 0.1 f c= 1 f ferrite bead = murata blm32a06 or equivalent +
a. hardware implementation 419 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com a.3.2 powerspan ii external p ll decoupling for new designs to provide the cleanest possible supply environment for the pll, the supplies shoul d be decoupled externally. isolation should be provided between the external core supply voltage on the board and the supply that goes to the pll. this can be done in the following ways: ? a separate core voltage regulator can be provide d and a separate trace run up to the pll supply pins. ? an isolation and decoupling network can be pr ovided for on the board to isolate and minimize noise on the core voltage supply plane be fore it gets to the pll supply pins. for optimum pll jitter performance , the pll should be isolated a nd decoupled from the main core power plane using a surface mount rf inductor and low esr tantalum surface mount capacitor network is recommended. the power supplies for plls on a device should come from a single point on the board. the power trace should then be isol ated from the main power plane using the network shown in figure 42 on page 419 . the routing parasitic resistance of the trace route from any pll supply pin to the decoupling capacitors in the isolation network must be less than 0.1 ohms. to minimize the tran sient ir drops across the leads from the isolation network and the pll supply de vice pins, the trace routes must be kept short. the preferred layout is to have the cripple capacitors, shown in figure 42 on page 419 , placed as close to the device pins as possible; potentially on the backside of the board underneath the device. figure 42: pll decoupling .0.5 ohms(min) 4 ohms(max) cfilter 4.7uf(min) 33uf(max) lfilter 470nh(min) 4.7uh(min) (rf smt) powerspan ii pll_avdd pll_dvdd cripple2 0.1uf pll_dvss pll_avss core vdd the vdd to vss 0.1uf decoupling caps must be as close to the device pins as possible. capacitors should be low esr (high frequency) ceramic chip capacitors. the trace routing and the rdc of the inductor accounts for this resistance and should be in the range shown. the trace routing resistance must be less than 0.1ohms to cripple1 and cripple2. cfilter must be a low esr tantalum smt capacitor. lfilter must be a high srf smt wire wound rf inductor. cripple1 0.1uf
a. hardware implementation 420 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com
421 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com b. typical applications this chapter describes typical applications for powerspan ii. ? ?overview? on page 421 ? ?winpath and powerspan ii applications? on page 427 ? ?winpath and powerspan ii applications? on page 427 b.1 overview the powerspan ii processor bus interface suppo rts motorola, ibm and wintegra embedded processors. in the following sections describe ty pical applications involv ing motorola and winpath processors. b.2 powerquicc ii and powerspan ii applications motorola?s family of embedded powerpc processo rs are widely used in the deployment of communications products. the intr oduction of the powerquicc ii, wi th its unsurpass ed levels of integration and performance, enhances the role of powerpc in communications systems. powerspan ii has a general purpose processor bus (pb) interf ace to motorola?s powerpc embedded processor family, which enables the design of pci based communication products. this section highlights the us e of powerspan ii in powerpc and compactpci applications. b.2.1 direct connect support the powerspan ii pb interface provides direct co nnect support for a number of powerpc embedded processors. the block diagram in figure 43 illustrates a system where the powerspan ii and the powerquicc ii and powerpc 7xx are directly connected. the powerquicc ii is a 64-bit bus master in this syst em. it can only interact with agents that have a 64-bit port size. since the powerpc 7xx does not ge nerate the extended transaction types of the powerquicc ii, it needs to be configured to meet powerquicc ii constraints. figure 43 illustrates the system where powerspan ii provides the following support: ? processor bus ? address and data bus arbitration ? processor bus master /slave capability ? single or dual pci access ? four channel dma
b. typical applications 422 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the powerspan ii pb interface full y supports the multi processing cache coherent aspects of the processor bus. the powerspan ii pb interface can on ly interact with 64-bit port size agents. the presence of the powerpc 7xx limi ts the extent of extended cycle su pport in the system depicted in figure 43 . figure 43: powerspan ii in multi-processor 60x system the siz[0] pin is hardwired on powerspan ii and the powerquicc ii. powerspan ii must operate with extended cycles disabled. it is stil l possible for the powe rquicc ii bus master to target sdram with extended cycles. powerspan pb_clk pb_br[3] pb_bg[3] pb_bg[2] pb_bg[1] pb_tsiz[1:3] pb_gbl, pb_ci pb_aack pb_d[0:63], pb_dp[0:7] pb_ta pb_dval pb_tea clock source clkin a[0:31], ap[0:3], tt[0:4], tbst tsiz[1:3] artry dh[0:31], dl[0:31], dp[0:7] br bg abb gbl, ci ts aack ape dbg dbb ta dval tea mpc8260 sysclk a[0:31], ap[0:3], tt[0:4], tbst dh[0:31], dl[0:31], dp[0:7] dpe tsiz[0:2] br bg abb gbl, ci ts artry aack ape dbg dbb ta tea drtry dbdis mpc740 2mx8 2mx8 a[10:0] address latch and mux sda10_gpl0 ale sdamux_gpl5 psdwe_gpl1 poe_sdras_gpl2 psdcas_gpl3 cso we_dqm_bs_b[0:7] 8 sdram a[0:31] pb_br[2] pb_br[1] pb_abb pb_dbg[3] pb_dbg[2] pb_dbg[1] pb_dbb pb_a[0:31], pb_ap[0:3], pb_tt[0:4], pb_tbst pb_ts pb_artry [1:3] tlbisync tsiz[0] pb_tsiz[0]
b. typical applications 423 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com the powerquicc ii is the system memory controller being used in this application in order to manage 64-bit wide sdram. the powerqui cc ii has processor bus master and slave capability. as a bus master in this system it can access sdram and pci. the address latch and multiplexor allow the external processor bus agents, the powerpc 7xx, and powerspan ii to access powerquicc ii controlled memory. additionally, the powerp c 7xx and powerspan ii can program powerquicc ii registers and master the powerquicc ii local bus. the powerspan ii processor bus arbiter controls system boot. boot can be selected from pci by configuring the arbiter at power-up to ignore all external requests on bus request (pb_br[3:1]_). this allows an external pci master to configure the powerquicc ii memory controller and load system boot code before enabling recogni tion of requests on pb_br[3:1]_. alternatively, at power-up the pro cessor bus arbiter is configured to recognize requests on pb_br[1]_ and ignore requests on pb_br[3:2] _. in this case the processor connected to pb_br[1]_ enables recognition of requests from other masters when its system configuration tasks are complete. b.2.2 compactpci adapter card a common powerspan ii application is the support of powerquicc ii based compactpci adapter cards. these cards are installed in peri pheral slots of the compactpci chassis. in figure 44 powerspan ii is in a dual powerquicc ii applic ation. one processor is selected to be the configuration master (rstconf_ is tied low) wh ile the second processor, and powerspan ii, are configuration slaves. optionally, the second processor could have the powerp c core disabled and be us ed strictly to provide more serial interface capability. powerspan ii?s pci-1 interface is de signated as the primary interface, through power-up option, and is connected to the compactpci backplane. it is poss ible to designate either pci-1 or pci-2 as the primary interface with a power-up option. the backpl ane supplies reset, clock and central resource functionality. the se condary pci interface, pci- 2, connects to a secondary pci system on the card and provides reset and arbitr ation for the secondary bus.
b. typical applications 424 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 44: powerspan ii in compactpci peripheral slot all powerspan ii resources are rese t when po_rst_ is asserted by the card?s power on reset logic. pb_rst_ and p2_rst# are configured as outputs and are asserted duri ng the power on reset sequence (po_rst_) or during a compactpci reset (p1_r st#). the connection between powerspan ii pb_rst_ and powerquicc ii hreset _is required for powerspan ii to load its power-up options during configuration activity gene rated by the configuration master. the adapter card has two basic configuration scenarios ? powerquicc ii system boots from local flash or from pci. p1_rst_dir p1_rst p1_inta p1_req[1] p1_gnt[1] p1_clk po_rst pb_rst pb_rst_dir int[0] pb_clk pb_rstconf i2c_sda i2c_sclk eeprom p2_clk p2_inta p2_gnt[2] p2_req[2] p2_gnt[1] p2_req[1] p2_rst p2_rst_dir powerspan compact pci p1/j1 connector rst# clk req# gnt# inta# rst# clk req# gnt# inta# secondary pci agents 66mhz 33mhz clock generataor and pll clkin rstconf hreset poreset clkin irq0 a[0:6] rstconf hreset poreset mpc8260 mpc8260 power on reset flash eeprom a[0] a[1] healthy board interrupts int[2] (master) (slave)
b. typical applications 425 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com when the powerquicc ii system boots from local flash there are two possible scenarios which can occur. in the first case, after reset, powerspan ii retries all accesses to its primary pci target. the powerquicc ii configures the powerspan ii primary and secondary base address registers and then configures all agents on the secondary bus. the powerquicc ii then enables accesses to the powerspan ii primary pci target. the compactpci host then comple tes the configuration of all primary pci agents. in the second scenario, an agent on the pci secondary bus config ures all agents there. the powerspan ii secondary pci target retries all accesses until the powerquicc ii completed configuration of powerspan ii secondary base address registers. b.2.3 compactpci host card powerspan ii supports the powerquicc ii as a ho st in a compactpci system. the application illustration, figure 45 , shows a directly connected powerspan ii in a powerqui cc ii system, which is supported by the powerpc 7xx. powerspan ii has reset and arbitration functionalit y for the primary and secondary pci bus segments. pb_rst_ is configured as an input while bot h p1_rst# and p2_rst# ar e outputs. a processor power-on reset or hard reset resets both primary and secondary pci bus segments. the card provides clocks for the embedded powerpcs, powerspan ii?s pb interface, all secondary pci agents, as well as the multiple clocks required for the compactpci backplane. powerspan ii?s bidirectional interrupt pins are used to handle all four compactpci interrupts and the hot swap system enumeration in terrupt. all interrupts are rout ed to the powerpc 7xx through powerspan ii pin int[5]_. the powerquicc ii system boots from local flash on the card. the powerquicc ii uses powerspan ii to configure all pci agents on the primary and secondary pci buses. powerspan ii supports system boot fro m pci with the processor bus arbiter.
b. typical applications 426 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com figure 45: powerspan ii in compactpci system slot a[1] a[0] powerspan power on reset flash eeprom rst# clk req64# req# gnt# inta# enum# rst# clk req64# req# gnt# inta# rst# clk req# gnt# inta# inta# rst# clk req# gnt# poreset hreset rstconf a[0:6] clkin poreset hreset rstconf clkin hreset int sysclk mpc740 clockgenerator and pll 66mhz 66mhz 33mhz 33mhz mpc8260 mpc8260 p1_rst_dir p1_rst int[0] int[1] int[2] int[3] int[4] p1_inta p1_req64 p1_req[1] p1_gnt[1] p1_req[2] pi_gnt[2] pi_req[3] pi_gnt[3] pi_req[4] pi_clk pb_clk int[5] p2_rst_dir p2_rst p2_req[1] p2_gnt[1] p2_req[2] p2_gnt[2] p2_inta p2_clk rst# clk req# gnt# inta# rst# clk req# gnt# inta# secondary pci agents peripheral slot 2 peripheral slot 3 peripheral slot 4 peripheral slot 5 compact pci p1/j1 connector inta# intb# intc# intd# compact pci peripheral slots pb_rstconf pb_rst_dir pb_rst po_rst pi_gnt[4] enum# (slave) healthy (master)
b. typical applications 427 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com b.3 winpath and powerspan ii applications detailed descriptions of typical appl ications, design information, signal connection, and register settin gs involving the wintegra winp ath processor and powerspan ii are available in the interfacing the wintegra wi npath with the idt powerspan ii application note.
b. typical applications 428 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com
429 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com glossary atpg automatic test pattern generation. address retry window refers to the clock following the assertion of aack_, which is the la test a snoopi ng master can request for an address tenure re-run. bar base address register. bd buffer descriptor each serial port in the powerquicc ii uses bds to indicate to the sdma channel the location of packet data in system memory. big-endian a byte ordering method in memory where the address of a word corresponds to the most significant byte. bist built-in self test. compactpci compactpci is an adaptation of the pci sp ecification for industrial and/or embedded applications requiring a more robust mech anical form factor than desktop pci. cycle cycle refers to a single data beat; a transa ction is composed of one or more cycles. ddm device driver module. a module th at abstracts the service of an i/o device and registers it as an i2o device. device an i/o object that refers to an i/o facility or service. adapters are the objects of hardware configuration, while logical devices are the objects of software configuration. dma direct memory access a process for transferring data from main memo ry to a device without passing it through the host processor. dram dynamic random access memory. dual pci powerspan ii powerspan ii variant with dual pci interfaces. flash writable non-volatile memory , often used to store code in embedded systems. host node a node composed of one or more application processors and thei r associated resources. host nodes execute a single homogeneous operating system and are dedi cated to processing applications. the host node is re sponsible for configuring and initializing the iop into the system.
glossary 430 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com host operating system the control program executing on the host. this may be the bios code, the host bootstrap code, or the final operating system for applic ation programs. also called the host or os. hot swap refers to the orderly insertion and extrac tion of compactpci boards without adversely affecting system operation. i2c inter-ic bus i2o intelligent i/o inbound queue a message queue of a particular i/o platform that receives messages from any sender (host or another iop). iop i/o platform a platform consisting of processor, memory, i/ o adapters and i/o devices. they are managed independently from other processors within the system, solely for processing i/o transactions. little-endian a byte ordering method in memory where the address of a word corresponds to the least significant byte master master (initiator) is the owner of the pci bus. it is used for both the processor (60x) bus and the pci bus. mf message frame mfa message frame address outbound queue a message queue for a specific i/o platform for posting messages to the local host, in lieu of the host?s inbound queue. powerpc 740 embedded powerpc processor. powerpc 750 embedded powerpc processor. powerpc 7400 embedded powerpc processor. powerquicc ii motorola integrated communications controller with 603ev powerpc core and external bus (also referred to as the mpc8260) prefetchable a range of memory space is prefetchable if there are no side effects on reads. peripheral slot slots on a compactpci bus segment that may c ontain simple boards, intelligent slaves, or pci bus masters.
glossary 431 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com pmc pci mezzanine card a mechanical format for adding pci based mezzanine cards to a vmebus card. primary pci interface adds extra functionality to the pci interface that is designated as the primary pci interface.the features are associated with the primary pci interface include: compactpci hot swap support, vital product data support and i 2 o shell interface. sdma serial dma used to support the movement of serial data to/from the serial ports of the powerquicc ii. secondary pci interface in the dual pci powerspan ii, this interface is the interface that is not designated as the primary pci interface. single pci powerspan ii powerspan ii variant with a single pci interface. slave slave (target) is the device wh ich is accessed by the bus master. it is used to refer to the address accessed by the master on the processor (60x) bus. strong ordering a memory access model that requires exclusiv e access to an address before making an update, to prevent another de vice from using stale data. system slot the slot on a compactpci bus segment that provi des arbitration, clock distribution, and reset functions for all boards on the segment target target (slave) is the device wh ich is accessed by the bus master. it is used to refer to the address accessed by the master on the pci bus. target image target image is a memory range which is mapped between the pci bus and the processor (60x) bus. weak ordering a memory access model that allows bus operations to be reordere d dynamically. this improves overall performance a nd reduces the effect of memory latency on instruction throughput. window of opportunity refers to the clock following the assertion of artry_. the retrying master has to request the bus on this clock to ensure that it is the next bus owner. this enables it to perform the transactions required to maintain cache coherency. winpath wintegra processor
glossary 432 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com
powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com 433 index numerics 42361 h1 chapter 14 ac timing 395 a ad[31:0] 196 , 199 address bus arbitration pb arbiter 142 address only cycles 143 address parity pb master 102 pb slave 91 pci target 41 address phase pb master 100 pb slave 85 pci master 47 pci target 37 address pipelining pb master 101 address retry window address bus tenure 89 defined 83 , 429 multi-processor environment 100 negating address bus request 101 pb slave terminations 99 address tenure pb slave 89 address translation pb master 102 pb slave 89 pci master 49 pci target 40 arbiters pci 137 system boot 143 arbitration 137 pb master 100 pci master 47 b bm 46 bm_park[2:0] 141 bus errors interrupts 146 pb master 111 pb slave 98 pci master 52 pci target 44 bus parking pb 100 , 142 pci 141 , 142 bus request pci bus 197 , 200 c c/be#[3:0] 196 , 199 cache coherency 101 chain 116 chip select 197 , 199 clean block 87 cline[1:0] 51 clocks pci 32 command encoding pci master 47 pci target 38 command packet contents 121 compactpci hot swap primary pci 32 concurrent reads 27 , 42 configuration cycle generation pci-to-pci 246 powerpc-to-pci 247 configuration read 48 configuration slave approach 175 configuration slave mode 175 configuration write 48 d d_pe 44 , 51 dact 116 data alignment pb master 106 pb slave 92 data bus arbitration and tenure pb master 103 pb slave 92 data parity pb master 110 pb slave 97 pci master 51 pci target 44 data phase pb master 103 pb slave 92 pci master 50 dest 42 devsel# 196 , 199 direct mode dma initializing 118 terminating 120 transfer acknowledgment 120 discard timer 97 dma
434 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com command packet addressing 115 command packet contents 121 direct mode 118 error handling 124 , 166 interrupts 124 linked-list mode 120 overview 26 register description 114 source and destination addresses 114 transfer control 115 dma controllers 113 document conventions numeric conventions 16 symbols 16 done 117 done_en 117 dual address cycle 48 e eeprom 127 overview 27 power-up 128 scl signal 202 sda signal 202 vital product data 60 , 135 eieio 88 electrical characteristics 381 , 417 end 179 endian mapping 177 big endian 183 conventions 177 little endian 185 munging/unmunging 181 powerpc little endian 179 , 187 powerpc to pci 183 register accesses 179 enid 201 error handling 157 dma 124 , 166 pb interface 158 pci interface 162 error logging and interrupts pb master 111 pb slave 99 pci master 52 pci target 45 even parity pb master 103 extcyc 111 extended cycles 104 f flush block 87 frame# 197 , 199 frequency pclk 197 , 200 qclk quicc 193 quicc idma fast termination 193 functional overview 19 g gnt# 197 , 199 go 116 h halt 116 halt_en 117 halt_req 116 hot swap card insertion 54 led 53 i i/o read 48 i/o write 48 i2c / eeprom interface 127 i2c_scl 127 i2o base address register 62 inbound messages 68 iop functionality 63 messaging interface 64 outbound messages 69 outbound option 73 pull capability 70 i2o shell interface primary pci 32 iack cycle generation pci-to-pci 246 powerpc-to-pci 247 icbi 88 idsel 197 , 199 int# 197 , 199 interrupt acknowledge 48 interrupts 145 dma 124 enabling 150 mapping 152 normal operations 145 pins 153 register description 147 sources 145 status 148 transfer exceptions 146 irdy# 197 , 199 k kill block 87
435 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com l last 121 linked-list mode dma initializing 122 terminating 124 loo 53 lwarx 88 m master interface pci 46 master-abort 52 max_retry 52 , 111 mdp_d 51 mechanical information 387 memory read 48 memory read line 48 memory read multiple 48 memory write 48 memory write and invalidate 48 mode 41 mra 43 munging/unmunging 181 n ncp[31:5] 121 non-transparent pci-to-pci 24 o odd parity pb master 103 pb slave 98 off 116 ordering information 415 p p1_err 116 p1_err_en 117 p1_r64_en 33 p2_err 116 p2_err_en 117 packaging information 387 par 197 , 199 parity monitoring and generation pci master 51 park 141 pb arbiters address bus arbitration 142 address only cycles 143 data bus arbitration 142 pb interface address phase 85 address retry window 83 , 429 bus errors 158 defined 83 overview 26 slave interface 84 terms 83 window of opportunity 83 , 431 pb master address bus arbitration and tenure 100 address parity 102 address phase 100 address pipelining 101 address translation 102 cache coherency 101 data alignment 106 data bus arbitration and tenure 103 data parity 110 data phase 103 terminations 111 transaction length 104 transaction mapping 102 window of opportunity 101 pb slave address parity 91 address tenure 89 data alignment 92 data parity 97 data phase 92 discard timer 97 errors 99 terminations 98 transaction length 92 writes 97 pb_err 116 pb_err_en 117 pci arbiters arbitration levels 138 bus parking 141 disabling 137 enabling 137 overview 137 pci interface 31 bus parking 141 , 142 clock frequencies 32 data width 32 errors 162 interface descriptions 34 overview 24 target interface 37 pci master address phase 47 address translation 49 arbitration 47 command encoding 47 data phase 50 error logging and interrupts 52 parity monitoring and generation 51 termination phase 52
436 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com pci target address parity 41 address phase 37 address translation 40 command encoding 38 data transfer 41 transaction code mapping 40 pclk 197 , 200 peresp 41 , 51 perr# 197 , 200 powerpc pb defined 83 power-up options configuration slave approach 175 pwrup_p1_arb_en 171 pwrup_p1_r64_en 32 pwrup_p2_arb_en 171 pwrup_pb_arb_en 171 pwrup_px_arb_en 140 primary pci defined 31 prkeep 44 , 96 processor bus interface 83 px_pb_err_en 51 r rd_amt[2:0] 43 , 96 read atomic 88 read with intent to modify 88 read with intent to modify atomic 88 read with no intent to cache 88 register accesses endian mapping 179 register map 76 registers dma x attributes register 117 dma x command packet pointer register 115 last 121 ncp[31:5] 121 dma x destination address register 115 dma x general control and status register chain 116 dack 116 done 117 done_en 117 go 116 halt 116 halt_en 117 halt_req 116 off 116 p1_err 116 p1_err_en 117 p2_err 116 p2_err_en 117 pb_err 116 pb_err_en 117 stop 116 stop_en 117 stop_req 116 dma x source address register 115 interrupt status register 0 148 , 150 interrupt status register 1 148 , 150 miscellaneous control and status register vpd_en 60 pci 1 compact pci hot swap control and status register loo 53 pci 1 control and status register bm 46 d_pe 44 , 51 mdp_d 51 peresp 41 , 44 , 51 r_ma 52 r_ta 52 s_ta 45 serr_en 41 pci 1 miscellane ous 0 register cline[1:0] 51 pci 1 miscellaneous cont rol and status register max_retry 52 pci 1 target image x base address register bar_en 39 bs[3:0] 39 ci_ 39 dest 39 end[1:0] 39 gbl_ 39 img_en 38 mode 39 mra 40 prkeep 39 rd_amt[2:0] 40 rtt[4:0] 39 ta_en 38 wtt[4:0] 39
437 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com pci 1 target image x control register dest 42 mra 43 prkeep 44 rd_amt[2:0] 43 ta_en 49 pci 1 vital product data capability register 60 pci 1 vital product data data register 60 pci x bus arbiter control register bm_park[2:0] 141 mx_pri 140 park 141 pci x target image x control register mode 41 rtt[4:0] 102 wtt[4:0] 102 pci x to pci y configurat ion cycle data register 246 pci x to pci y configuration cycle information register 246 pci x to pci y interrupt acknowledge cycle generation register 246 pci-1 control and status register dev66 32 processor bus miscellaneous control and status register extcyc 111 max_retry 111 processor bus pci configuration cycle information register 247 processor bus register image base address register end 179 processor bus slave image x control register bs[4:0] 86 dest 86 end[1:0] 86 img_en 86 mode 86 prkeep 86 , 96 rd_amt[2:0] 86 , 96 ta_en 86 reset control and status register p1_r64_en 33 req# 197 , 200 reset from pci bus 198 , 200 timing parameters 398 , 399 , 404 , 405 resets direction control 167 generation 169 pins 167 rst# 198 , 200 rtt[4:0] 102 s scl 202 sda 202 serr_en 41 serr# 198 , 200 signal descriptions 191 signals aack 83 , 429 ad[31:0] 51 artry 83 , 101 , 431 description 191 enum 53 healthy 53 , 167 int[5:0] 153 interrupts 153 led 53 miscellaneous 201 p1_64en 33 , 53 p1_inta 153 p1_req64 32 p1_rst 33 , 167 p1_rst_dir 168 p2_inta 153 p2_rst 167 p2_rst_dir 168 pb_a[] 85 pb_aack 87 , 89 , 100 pb_abb 100 pb_artry 89 , 98 , 100 , 103 , 111 pb_bg 101 pb_ci 86 , 101 , 117 pb_dbb 103 pb_dp[0:7] 98 , 110 pb_dval 98 , 111 pb_gbl 86 , 101 , 117 pb_rst 167 pb_rst_dir 168 pb_ta 98 , 111 pb_tea 111 pb_ts 89 , 103 pb_tt[] 85 pci-1 196 pci-2 199 po_rst 167 powerpc (pb) 192 px_ad[31:0] 44 px_c be[3:0] 44 , 51 px_devsel 52 px_frame 52 px_irdy 52 px_m66en 32 px_par 44 , 51 px_perr 51 px_trdy 52 test 203 siz[1:0] 195 special cycle 48 stop 116 stop_en 117
438 powerspan ii user manual 80a1010_ma001_09 integrated device technology www.idt.com stop_req 116 stop# 196 , 197 , 198 , 200 sync block 87 system boot 143 t target-abort 52 target-disconnect 41 , 52 target-retry 52 termination phase pb master 111 pb slave 98 pci master 52 pci target 44 test signals 203 tlb invalidate 88 tlb sync 88 transaction length pb master 104 pb slave 92 transaction mapping pb master 102 pci master 48 pci target 40 trdy# 198 , 200 , 203 , 204 typical applications 421 v vital product data defined 60 eeprom 60 primary pci 32 reading 60 writing 61 vpd_en 60 w window of opportunity 101 defined 83 , 431 write with flush 41 write with flush 88 write with flush atomic 88 write with kill 88 wtt[4:0] 102
corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: ehbhelp@idt.com phone: 408-360-1538 document: 80a1010_ma001_09 november 2009 ? 2009 integrated device technology, inc *notice: the information in this docume nt is subject to change without notice disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, wh ether express or implied, including, but not limited to, the suit ability of idt?s products for any particular purpose, an impli ed warranty of merchantability, or non-infringe ment of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2009. all rights reserved.

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